[PATCH 01/10] drm/amd/amdgpu: Add offset variant to SOC15 macros

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Am 12.06.2017 um 19:54 schrieb Tom St Denis:
> Allows reading/writing via SOC15 macros with offset for
> various register banks.
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>

Acked-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/soc15_common.h | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index e8df6d820dbe..e2d330eed952 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -63,6 +63,13 @@ struct nbio_pcie_index_data {
>   		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>   		(ip##_BASE__INST##inst##_SEG4 + reg))))))
>   
> +#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
> +	RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset)
> +
>   #define WREG32_SOC15(ip, inst, reg, value) \
>   	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
>   		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> @@ -70,6 +77,13 @@ struct nbio_pcie_index_data {
>   		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>   		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
>   
> +#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
> +	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> +		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> +		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> +		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> +		(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value)
> +
>   #endif
>   
>   




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