OK. Regards, Shirish S ________________________________ From: Deucher, Alexander Sent: Friday, June 9, 2017 6:23:12 PM To: S, Shirish; amd-gfx at lists.freedesktop.org; Alex Deucher Subject: RE: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts Please include patch 1 of this series as well. From: S, Shirish Sent: Friday, June 09, 2017 8:53 AM To: amd-gfx at lists.freedesktop.org; Alex Deucher Cc: Deucher, Alexander Subject: Re: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts Sure Alex. I shall update the result on stoney soon. Regards, Shirish S ________________________________ From: Alex Deucher <alexdeucher@xxxxxxxxx<mailto:alexdeucher at gmail.com>> Sent: Friday, June 9, 2017 6:19:30 PM To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> Cc: Deucher, Alexander; S, Shirish Subject: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts Now that interrupts are properly enabled for all pipes, this should be function properly. Cc: Shirish S <shirish.s at amd.com<mailto:shirish.s at amd.com>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com<mailto:alexander.deucher at amd.com>> --- Shirish, Can you test this change on your Stoney setup? drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index dfbf027..03c23e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -125,15 +125,9 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) if (mec >= adev->gfx.mec.num_mec) break; - if (adev->gfx.mec.num_mec > 1) { - /* policy: amdgpu owns the first two queues of the first MEC */ - if (mec == 0 && queue < 2) - set_bit(i, adev->gfx.mec.queue_bitmap); - } else { - /* policy: amdgpu owns all queues in the first pipe */ - if (mec == 0 && pipe == 0) - set_bit(i, adev->gfx.mec.queue_bitmap); - } + /* policy: amdgpu owns the first two queues of the first MEC */ + if (mec == 0 && queue < 2) + set_bit(i, adev->gfx.mec.queue_bitmap); } /* update the number of active compute rings */ -- 2.5.5 -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20170609/fbae2c32/attachment-0001.html>
