Hi Christian, Sorry, it's my first time to submit code to the staging. I have done the fix. Attached the fixed review. Thank you for the review. Regards, Horace. -----Original Message----- From: Christian König [mailto:deathsimple@xxxxxxxxxxx] Sent: Friday, June 09, 2017 8:25 PM To: Chen, Horace; amd-gfx at lists.freedesktop.org Cc: Huang, Ray Subject: Re: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create Am 09.06.2017 um 13:59 schrieb horchen: > Under VF environment, the ucode would be settled to the visible VRAM, > As it would be pinned to the visible VRAM, it's better to add > contiguous flag,otherwise it need to move gpu address during the pin > process. This movement is not necessary. > > Signed-off-by: horchen <horace.chen at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > index cd6d3d0..3b1ee05 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c > @@ -379,7 +379,8 @@ int amdgpu_ucode_init_bo(struct amdgpu_device > *adev) > > err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, > amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, > - 0, NULL, NULL, bo); > + amdgpu_sriov_vf(adev) ? AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS : 0, > + NULL, NULL, bo); Mhm, did you missed my comment? You can add the AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS unconditionally here, e.g. without checking amdgpu_sriov_vf(adev). With that fixed the patch is Reviewed-by: Christian König <christian.koenig at amd.com>. > if (err) { > dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); > goto failed; -------------- next part -------------- An embedded message was scrubbed... From: "Chen, Horace" <Horace.Chen@xxxxxxx> Subject: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create Date: Fri, 9 Jun 2017 13:42:32 +0000 Size: 4285 URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20170609/c78a7b41/attachment.mht>
