Am 09.06.2017 um 00:06 schrieb Andres Rodriguez:
> The AMDGPU_SCHED_OP_PROCESS_PRIORITY_GET/PUT ioctls are used to set the
> priority of a different process in the current system.
>
> When all requests are dropped, the foreign process's contexts will be
> restored to the priority specified at context creation time.
>
> An fd is used to identify the remote process. This is simpler than
> passing a pid number, which is vulnerable to re-use, etc.
>
> This functionality is limited to DRM_MASTER since abuse of this
> interface can have a negative impact on the system's performance.
>
> Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 +----
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 117 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h | 34 +++++++++
> include/uapi/drm/amdgpu_drm.h | 25 +++++++
> 6 files changed, 180 insertions(+), 19 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index b62d9e9..e4d3b07 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -13,31 +13,31 @@ ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
>
> amdgpu-y := amdgpu_drv.o
>
> # add KMS driver
> amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \
> atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \
> amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \
> amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \
> amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \
> amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \
> atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
> amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
> amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
> amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
> - amdgpu_queue_mgr.o
> + amdgpu_queue_mgr.o amdgpu_sched.o
>
> # add asic specific block
> amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
> ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
> amdgpu_amdkfd_gfx_v7.o
>
> amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
>
> amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o
>
> # add GMC block
> amdgpu-y += \
> gmc_v7_0.o \
> gmc_v8_0.o \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index cc15b7e..a578557 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -12,30 +12,31 @@
> * all copies or substantial portions of the Software.
> *
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> *
> * Authors: monk liu <monk.liu at amd.com>
> */
>
> #include <drm/drmP.h>
> #include "amdgpu.h"
> +#include "amdgpu_sched.h"
>
> static amdgpu_ctx_priority_permit(struct drm_file *filp,
> enum amd_sched_priority priority)
> {
> /* NORMAL and below are accessible by everyone */
> if (priority <= AMD_SCHED_PRIORITY_NORMAL)
> return 0;
>
> if (capable(CAP_SYS_NICE))
> return 0;
>
> if (drm_is_current_master(filp))
> return 0;
>
> return -EACCES;
> @@ -234,48 +235,30 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
> out->state.hangs = 0x0;
>
> /* determine if a GPU reset has occured since the last call */
> reset_counter = atomic_read(&adev->gpu_reset_counter);
> /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
> if (ctx->reset_counter == reset_counter)
> out->state.reset_status = AMDGPU_CTX_NO_RESET;
> else
> out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
> ctx->reset_counter = reset_counter;
>
> mutex_unlock(&mgr->lock);
> return 0;
> }
>
> -static enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
> -{
> - switch (amdgpu_priority) {
> - case AMDGPU_CTX_PRIORITY_HIGH_HW:
> - return AMD_SCHED_PRIORITY_HIGH_HW;
> - case AMDGPU_CTX_PRIORITY_HIGH_SW:
> - return AMD_SCHED_PRIORITY_HIGH_SW;
> - case AMDGPU_CTX_PRIORITY_NORMAL:
> - return AMD_SCHED_PRIORITY_NORMAL;
> - case AMDGPU_CTX_PRIORITY_LOW_SW:
> - case AMDGPU_CTX_PRIORITY_LOW_HW:
> - return AMD_SCHED_PRIORITY_LOW;
> - default:
> - WARN(1, "Invalid context priority %d\n", amdgpu_priority);
> - return AMD_SCHED_PRIORITY_INVALID;
> - }
> -}
> -
> int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp)
> {
> int r;
> uint32_t id;
> enum amd_sched_priority priority;
>
> union drm_amdgpu_ctx *args = data;
> struct amdgpu_device *adev = dev->dev_private;
> struct amdgpu_fpriv *fpriv = filp->driver_priv;
>
> r = 0;
> id = args->in.ctx_id;
> priority = amdgpu_to_sched_priority(args->in.priority);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 92e93b3..6a33c61 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -16,30 +16,31 @@
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> *
> * Authors: Dave Airlie
> * Alex Deucher
> * Jerome Glisse
> */
> #include <drm/drmP.h>
> #include "amdgpu.h"
> #include <drm/amdgpu_drm.h>
> +#include "amdgpu_sched.h"
> #include "amdgpu_uvd.h"
> #include "amdgpu_vce.h"
>
> #include <linux/vga_switcheroo.h>
> #include <linux/slab.h>
> #include <linux/pm_runtime.h>
> #include "amdgpu_amdkfd.h"
>
> /**
> * amdgpu_driver_unload_kms - Main unload function for KMS.
> *
> * @dev: drm dev pointer
> *
> * This is the main unload function for KMS (all asics).
> * Returns 0 on success.
> @@ -1004,30 +1005,31 @@ int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
> *
> * Disable the interrupt on the requested crtc (all asics).
> */
> void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
> {
> struct amdgpu_device *adev = dev->dev_private;
> int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
>
> amdgpu_irq_put(adev, &adev->crtc_irq, idx);
> }
>
> const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
> DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> /* KMS */
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> };
> const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
> new file mode 100644
> index 0000000..eacce6f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
> @@ -0,0 +1,117 @@
> +/*
> + * Copyright 2017 Valve Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: Andres Rodriguez <andresx7 at gmail.com>
> + */
> +
> +#include <linux/fdtable.h>
> +#include <linux/pid.h>
> +#include <drm/amdgpu_drm.h>
> +#include "amdgpu.h"
> +
> +#include "amdgpu_vm.h"
> +
> +enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
> +{
> + switch (amdgpu_priority) {
> + case AMDGPU_CTX_PRIORITY_HIGH_HW:
> + return AMD_SCHED_PRIORITY_HIGH_HW;
> + case AMDGPU_CTX_PRIORITY_HIGH_SW:
> + return AMD_SCHED_PRIORITY_HIGH_SW;
> + case AMDGPU_CTX_PRIORITY_NORMAL:
> + return AMD_SCHED_PRIORITY_NORMAL;
> + case AMDGPU_CTX_PRIORITY_LOW_SW:
> + case AMDGPU_CTX_PRIORITY_LOW_HW:
> + return AMD_SCHED_PRIORITY_LOW;
> + default:
> + WARN(1, "Invalid context priority %d\n", amdgpu_priority);
> + return AMD_SCHED_PRIORITY_INVALID;
> + }
> +}
> +
> +static int amdgpu_sched_process_priority_ref(struct amdgpu_device *adev,
> + int fd,
> + enum amd_sched_priority priority,
> + bool acquire)
> +{
> + struct file *filp = fcheck(fd);
> + struct drm_file *file;
> + struct pid *pid;
> + struct amdgpu_fpriv *fpriv;
> + struct amdgpu_ctx *ctx;
> + uint32_t id;
> +
> + if (!filp)
> + return -EINVAL;
> +
> + pid = get_pid(((struct drm_file *)filp->private_data)->pid);
> +
> + mutex_lock(&adev->ddev->filelist_mutex);
> + list_for_each_entry(file, &adev->ddev->filelist, lhead) {
> + if (file->pid != pid)
> + continue;
> +
> + fpriv = file->driver_priv;
> + idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
> + if (acquire)
> + amdgpu_ctx_priority_get(ctx, priority);
> + else
> + amdgpu_ctx_priority_put(ctx, priority);
> + }
> + mutex_unlock(&adev->ddev->filelist_mutex);
> +
> + put_pid(pid);
> +
> + return 0;
> +}
> +
> +int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *filp)
> +{
> + union drm_amdgpu_sched *args = data;
> + struct amdgpu_device *adev = dev->dev_private;
> + enum amd_sched_priority priority;
> + int r;
> +
> + priority = amdgpu_to_sched_priority(args->in.priority);
> + if (args->in.reserved || priority == AMD_SCHED_PRIORITY_INVALID)
> + return -EINVAL;
> +
> + switch (args->in.op) {
> + case AMDGPU_SCHED_OP_PROCESS_PRIORITY_GET:
> + r = amdgpu_sched_process_priority_ref(adev,
> + args->in.fd,
> + priority,
> + true);
> + break;
> + case AMDGPU_SCHED_OP_PROCESS_PRIORITY_PUT:
> + r = amdgpu_sched_process_priority_ref(adev,
> + args->in.fd,
> + priority,
> + false);
> + break;
> + default:
> + r = -EINVAL;
> + break;
> + }
> +
> + return r;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
> new file mode 100644
> index 0000000..b28c067
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
> @@ -0,0 +1,34 @@
> +/*
> + * Copyright 2017 Valve Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: Andres Rodriguez <andresx7 at gmail.com>
> + */
> +
> +#ifndef __AMDGPU_SCHED_H__
> +#define __AMDGPU_SCHED_H__
> +
> +#include <drm/drmP.h>
> +
> +enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority);
> +int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *filp);
> +
> +#endif // __AMDGPU_SCHED_H__
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 590fc2a..99eb946 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -40,45 +40,47 @@ extern "C" {
>
> #define DRM_AMDGPU_GEM_CREATE 0x00
> #define DRM_AMDGPU_GEM_MMAP 0x01
> #define DRM_AMDGPU_CTX 0x02
> #define DRM_AMDGPU_BO_LIST 0x03
> #define DRM_AMDGPU_CS 0x04
> #define DRM_AMDGPU_INFO 0x05
> #define DRM_AMDGPU_GEM_METADATA 0x06
> #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
> #define DRM_AMDGPU_GEM_VA 0x08
> #define DRM_AMDGPU_WAIT_CS 0x09
> #define DRM_AMDGPU_GEM_OP 0x10
> #define DRM_AMDGPU_GEM_USERPTR 0x11
> #define DRM_AMDGPU_WAIT_FENCES 0x12
> #define DRM_AMDGPU_VM 0x13
> +#define DRM_AMDGPU_SCHED 0x14
>
> #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
> #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
> #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
> #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
> #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
> #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
> #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
> #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
> #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
> #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
> #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
> #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
> #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
> +#define DRM_IOCTL_AMDGPU_SCHED DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
>
> #define AMDGPU_GEM_DOMAIN_CPU 0x1
> #define AMDGPU_GEM_DOMAIN_GTT 0x2
> #define AMDGPU_GEM_DOMAIN_VRAM 0x4
> #define AMDGPU_GEM_DOMAIN_GDS 0x8
> #define AMDGPU_GEM_DOMAIN_GWS 0x10
> #define AMDGPU_GEM_DOMAIN_OA 0x20
>
> /* Flag that CPU access will be required for the case of VRAM domain */
> #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
> /* Flag that CPU access will not work, this VRAM domain is invisible */
> #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
> /* Flag that USWC attributes should be used for GTT */
> #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
> /* Flag that the memory should be in VRAM and cleared */
> @@ -208,30 +210,53 @@ struct drm_amdgpu_vm_in {
> /** AMDGPU_VM_OP_* */
> __u32 op;
> __u32 flags;
> };
>
> struct drm_amdgpu_vm_out {
> /** For future use, no flags defined so far */
> __u64 flags;
> };
>
> union drm_amdgpu_vm {
> struct drm_amdgpu_vm_in in;
> struct drm_amdgpu_vm_out out;
> };
>
> +/* sched ioctl */
> +#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_GET 1
> +#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_PUT 2
> +
> +struct drm_amdgpu_sched_in {
> + /* AMDGPU_SCHED_OP_* */
> + __u32 op;
> + __u32 fd;
> + __s32 priority;
> + /* For future use */
> + __u32 reserved;
Even if you don't define one, call that flags not reserved.
> +};
> +
> +struct drm_amdgpu_sched_out {
> + /* For future use */
> + __u64 reserved;
> +};
If you don't have an out parameter, don't add a dummy structure and
declare the IOCTL DRM_IOW instead of DRM_IORW.
Regards,
Christian.
> +
> +union drm_amdgpu_sched {
> + struct drm_amdgpu_sched_in in;
> + struct drm_amdgpu_sched_out out;
> +};
> +
> /*
> * This is not a reliable API and you should expect it to fail for any
> * number of reasons and have fallback path that do not use userptr to
> * perform any operation.
> */
> #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
> #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
> #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
> #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
>
> struct drm_amdgpu_gem_userptr {
> __u64 addr;
> __u64 size;
> /* AMDGPU_GEM_USERPTR_* */
> __u32 flags;
