Hi Alex,
In closed source driver, we assign compute queues to all 4 pipes always.
There is no hangs.
May I know which ASIC?
Assign all queues in first pipe first mec can slow things down.
Thanks,
Alex Bin Xie
On 2017-06-07 11:10 AM, Alex Deucher wrote:
> Fixes hangs on single MEC asics.
>
> Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of each pipe v2)
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 12 +++++++++---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++++++++---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++++---
> 3 files changed, 27 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 4c04e9d..862bc72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2825,9 +2825,15 @@ static void gfx_v7_0_compute_queue_acquire(struct amdgpu_device *adev)
> if (mec >= adev->gfx.mec.num_mec)
> break;
>
> - /* policy: amdgpu owns the first two queues of the first MEC */
> - if (mec == 0 && queue < 2)
> - set_bit(i, adev->gfx.mec.queue_bitmap);
> + if (adev->gfx.mec.num_mec > 1) {
> + /* policy: amdgpu owns the first two queues of the first MEC */
> + if (mec == 0 && queue < 2)
> + set_bit(i, adev->gfx.mec.queue_bitmap);
> + } else {
> + /* policy: amdgpu owns all queues in the first pipe */
> + if (mec == 0 && pipe == 0)
> + set_bit(i, adev->gfx.mec.queue_bitmap);
> + }
> }
>
> /* update the number of active compute rings */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index ad2e0bb..1370b39 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1464,9 +1464,15 @@ static void gfx_v8_0_compute_queue_acquire(struct amdgpu_device *adev)
> if (mec >= adev->gfx.mec.num_mec)
> break;
>
> - /* policy: amdgpu owns the first two queues of the first MEC */
> - if (mec == 0 && queue < 2)
> - set_bit(i, adev->gfx.mec.queue_bitmap);
> + if (adev->gfx.mec.num_mec > 1) {
> + /* policy: amdgpu owns the first two queues of the first MEC */
> + if (mec == 0 && queue < 2)
> + set_bit(i, adev->gfx.mec.queue_bitmap);
> + } else {
> + /* policy: amdgpu owns all queues in the first pipe */
> + if (mec == 0 && pipe == 0)
> + set_bit(i, adev->gfx.mec.queue_bitmap);
> + }
> }
>
> /* update the number of active compute rings */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index cf15a350..9d675b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -873,9 +873,15 @@ static void gfx_v9_0_compute_queue_acquire(struct amdgpu_device *adev)
> if (mec >= adev->gfx.mec.num_mec)
> break;
>
> - /* policy: amdgpu owns the first two queues of the first MEC */
> - if (mec == 0 && queue < 2)
> - set_bit(i, adev->gfx.mec.queue_bitmap);
> + if (adev->gfx.mec.num_mec > 1) {
> + /* policy: amdgpu owns the first two queues of the first MEC */
> + if (mec == 0 && queue < 2)
> + set_bit(i, adev->gfx.mec.queue_bitmap);
> + } else {
> + /* policy: amdgpu owns all queues in the first pipe */
> + if (mec == 0 && pipe == 0)
> + set_bit(i, adev->gfx.mec.queue_bitmap);
> + }
> }
>
> /* update the number of active compute rings */
