Disable ecc by default
Signed-off-by: Junwei Zhang <Jerry.Zhang at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 60 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 2 ++
3 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index b04cc80..ec433b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -52,6 +52,8 @@ static int psp_sw_init(void *handle)
switch (adev->asic_type) {
case CHIP_VEGA10:
psp->init_microcode = psp_v3_1_init_microcode;
+ psp->bootloader_is_sos_running = psp_v3_1_bootloader_is_sos_running;
+ psp->bootloader_set_ecc_mode = psp_v3_1_bootloader_set_ecc_mode;
psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
@@ -61,6 +63,7 @@ static int psp_sw_init(void *handle)
psp->cmd_submit = psp_v3_1_cmd_submit;
psp->compare_sram_data = psp_v3_1_compare_sram_data;
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+ psp->config.ecc_mode = PSP_ECC_MODE__NONE;
break;
case CHIP_RAVEN:
#if 0
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f93a66e..0a51dde 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -162,6 +162,66 @@ int psp_v3_1_init_microcode(struct psp_context *psp)
return err;
}
+bool psp_v3_1_bootloader_is_sos_running(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+
+ if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81) != 0)
+ return true;
+ else
+ return false;
+}
+
+int psp_v3_1_bootloader_set_ecc_mode(struct psp_context *psp)
+{
+ int ret = 0;
+ uint32_t sol_reg;
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t psp_gfxdrv_command_reg = 0;
+
+ /* Workaround: check bootloader version and skip old one */
+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+ if (sol_reg < 0xB0C00)
+ return ret;
+
+ switch (psp->config.ecc_mode)
+ {
+ case PSP_ECC_MODE__NONE:
+ break;
+ case PSP_ECC_MODE__OFF:
+ psp_gfxdrv_command_reg = PSP_BL__NO_ECC;
+ break;
+ case PSP_ECC_MODE__ON:
+ psp_gfxdrv_command_reg = PSP_BL__FULL_ECC;
+ break;
+ case PSP_ECC_MODE__PARTIALON:
+ psp_gfxdrv_command_reg = PSP_BL__PARTIAL_ECC;
+ break;
+ default:
+ break;
+ }
+
+ if (psp_gfxdrv_command_reg == 0)
+ return ret;
+
+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x80000000, 0x80000000, false);
+ if (ret)
+ return ret;
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg);
+
+ /* There might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x80000000, 0x80000000, false);
+
+ return ret;
+}
+
int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
{
int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
index 9dcd0b2..3e52b5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
@@ -34,6 +34,8 @@
extern int psp_v3_1_init_microcode(struct psp_context *psp);
extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
+extern bool psp_v3_1_bootloader_is_sos_running(struct psp_context *psp);
+extern int psp_v3_1_bootloader_set_ecc_mode(struct psp_context *psp);
extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd);
--
1.9.1
