Am 25.07.2017 um 05:30 schrieb Alex Deucher:
> Needs to be done when the MC is set up.
>
> v2: make consistent with other asics
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
On first glance it kind of looks a bit odd to have that in the GMC code,
but on second glance it actually makes sense.
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 117c4835..ab0a104 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -249,7 +249,19 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
> dev_warn(adev->dev, "Wait for MC idle timedout !\n");
> }
>
> - WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
> + if (adev->mode_info.num_crtc) {
> + u32 tmp;
> +
> + /* Lockout access through VGA aperture*/
> + tmp = RREG32(mmVGA_HDP_CONTROL);
> + tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
> + WREG32(mmVGA_HDP_CONTROL, tmp);
> +
> + /* disable VGA render */
> + tmp = RREG32(mmVGA_RENDER_CONTROL);
> + tmp &= ~VGA_VSTATUS_CNTL;
> + WREG32(mmVGA_RENDER_CONTROL, tmp);
> + }
> /* Update configuration */
> WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> adev->mc.vram_start >> 12);
