[PATCH 2/2] drm/amdgpu: Clear active for HIQ in RLC_CP_SCHEDULER

[Tom.StDenis@xxxxxxx (StDenis, Tom)]

You could use WREG32_FIELD15 to drop 3 lines into one.

Tom
________________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Shaoyun Liu <Shaoyun.Liu at amd.com>
Sent: Wednesday, July 19, 2017 16:26
To: amd-gfx at lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH 2/2] drm/amdgpu: Clear active for HIQ in RLC_CP_SCHEDULER

Change-Id: I780e276983ba5a3bf077d274c84eb168585c806a
Signed-off-by: Shaoyun Liu <Shaoyun.Liu at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 11 +++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 12 ++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index cb41b54..5fa2f8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -619,9 +619,20 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
        enum hqd_dequeue_request_type type;
        unsigned long flags, end_jiffies;
        int retry;
+       struct vi_mqd *m;
+
+       m = get_mqd(mqd);

        acquire_queue(kgd, pipe_id, queue_id);

+       if (m->cp_hqd_vmid == 0) {
+               uint32_t value;
+
+               value = RREG32(mmRLC_CP_SCHEDULERS);
+               value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 0);
+               WREG32(mmRLC_CP_SCHEDULERS, value);
+       }
+
        switch (reset_type) {
        case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
                type = DRAIN_PIPE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 2f36d11..d47cdff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -754,14 +754,26 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        enum hqd_dequeue_request_type type;
        unsigned long end_jiffies;
+       struct v9_mqd *m;
        uint32_t temp;
+
 #if 0
        unsigned long flags;
        int retry;
 #endif
+       m = get_mqd(mqd);

        acquire_queue(kgd, pipe_id, queue_id);

+       if (m->cp_hqd_vmid == 0) {
+               uint32_t value;
+
+               value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
+               value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 0);
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
+       }
+
+
        switch (reset_type) {
        case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
                type = DRAIN_PIPE;
--
1.9.1

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