Am 12.07.2017 um 04:48 schrieb zhoucm1:
>
>
> On 2017å¹´07æ??12æ?¥ 03:30, Alex Deucher wrote:
>> On Mon, Jul 10, 2017 at 5:15 PM, Alex Deucher <alexdeucher at gmail.com>
>> wrote:
>>> The information has moved to different tables, notably
>>> smu_info for core refclk and umc_info for mem refclk.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>> ping? this fixes looking up the reference clocks on vega10 and raven.
> The both two are Acked-by: Chunming Zhou <david1.zhou at amd.com>
Acked-by: Christian König <christian.koenig at amd.com> as well.
I think somebody else should dig into the AtomBIOS/AtomFirmware stuff as
well, otherwise Alex becomes our single point of failure one more (ok
that sounds funny, but I think you know what I mean).
Christian.
>>
>> Alex
>>
>>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 93
>>> ++++++++++++++++++++++++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 1 +
>>> 2 files changed, 94 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> index a7d65f0..f9ffe8e 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> @@ -128,3 +128,96 @@ int amdgpu_atomfirmware_get_vram_width(struct
>>> amdgpu_device *adev)
>>>
>>> return 0;
>>> }
>>> +
>>> +union firmware_info {
>>> + struct atom_firmware_info_v3_1 v31;
>>> +};
>>> +
>>> +union smu_info {
>>> + struct atom_smu_info_v3_1 v31;
>>> +};
>>> +
>>> +union umc_info {
>>> + struct atom_umc_info_v3_1 v31;
>>> +};
>>> +
>>> +int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
>>> +{
>>> + struct amdgpu_mode_info *mode_info = &adev->mode_info;
>>> + struct amdgpu_pll *spll = &adev->clock.spll;
>>> + struct amdgpu_pll *mpll = &adev->clock.mpll;
>>> + uint8_t frev, crev;
>>> + uint16_t data_offset;
>>> + int ret = -EINVAL, index;
>>> +
>>> + index =
>>> get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
>>> + firmwareinfo);
>>> + if (amdgpu_atom_parse_data_header(mode_info->atom_context,
>>> index, NULL,
>>> + &frev, &crev, &data_offset)) {
>>> + union firmware_info *firmware_info =
>>> + (union firmware_info
>>> *)(mode_info->atom_context->bios +
>>> + data_offset);
>>> +
>>> + adev->clock.default_sclk =
>>> + le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
>>> + adev->clock.default_mclk =
>>> + le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
>>> +
>>> + adev->pm.current_sclk = adev->clock.default_sclk;
>>> + adev->pm.current_mclk = adev->clock.default_mclk;
>>> +
>>> + /* not technically a clock, but... */
>>> + adev->mode_info.firmware_flags =
>>> + le32_to_cpu(firmware_info->v31.firmware_capability);
>>> +
>>> + ret = 0;
>>> + }
>>> +
>>> + index =
>>> get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
>>> + smu_info);
>>> + if (amdgpu_atom_parse_data_header(mode_info->atom_context,
>>> index, NULL,
>>> + &frev, &crev, &data_offset)) {
>>> + union smu_info *smu_info =
>>> + (union smu_info
>>> *)(mode_info->atom_context->bios +
>>> + data_offset);
>>> +
>>> + /* system clock */
>>> + spll->reference_freq =
>>> le32_to_cpu(smu_info->v31.core_refclk_10khz);
>>> +
>>> + spll->reference_div = 0;
>>> + spll->min_post_div = 1;
>>> + spll->max_post_div = 1;
>>> + spll->min_ref_div = 2;
>>> + spll->max_ref_div = 0xff;
>>> + spll->min_feedback_div = 4;
>>> + spll->max_feedback_div = 0xff;
>>> + spll->best_vco = 0;
>>> +
>>> + ret = 0;
>>> + }
>>> +
>>> + index =
>>> get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
>>> + umc_info);
>>> + if (amdgpu_atom_parse_data_header(mode_info->atom_context,
>>> index, NULL,
>>> + &frev, &crev, &data_offset)) {
>>> + union umc_info *umc_info =
>>> + (union umc_info
>>> *)(mode_info->atom_context->bios +
>>> + data_offset);
>>> +
>>> + /* memory clock */
>>> + mpll->reference_freq =
>>> le32_to_cpu(umc_info->v31.mem_refclk_10khz);
>>> +
>>> + mpll->reference_div = 0;
>>> + mpll->min_post_div = 1;
>>> + mpll->max_post_div = 1;
>>> + mpll->min_ref_div = 2;
>>> + mpll->max_ref_div = 0xff;
>>> + mpll->min_feedback_div = 4;
>>> + mpll->max_feedback_div = 0xff;
>>> + mpll->best_vco = 0;
>>> +
>>> + ret = 0;
>>> + }
>>> +
>>> + return ret;
>>> +}
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>>> index cedafbb..288b97e 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>>> @@ -28,5 +28,6 @@ bool
>>> amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device
>>> *adev)
>>> void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device
>>> *adev);
>>> int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device
>>> *adev);
>>> int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
>>> +int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
>>>
>>> #endif
>>> --
>>> 2.5.5
>>>
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>
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