> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Evan Quan > Sent: Thursday, July 06, 2017 9:59 PM > To: amd-gfx at lists.freedesktop.org > Cc: Deucher, Alexander; Quan, Evan > Subject: [PATCH 6/6] drm/amd/powerplay: added didt support for vega10 > > Change-Id: If2f955469e5b037e0726999b10eb10c08740b208 > Signed-off-by: Evan Quan <evan.quan at amd.com> Series is: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 56 + > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 5 + > .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 1291 > ++++++++++++++++++++ > .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 16 + > .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 5 + > drivers/gpu/drm/amd/powerplay/inc/pp_debug.h | 6 + > drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 2 + > 7 files changed, 1381 insertions(+) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index 780efaf..ae11d30 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -145,6 +145,19 @@ static void vega10_set_default_registry_data(struct > pp_hwmgr *hwmgr) > data->registry_data.vr1hot_enabled = 1; > data->registry_data.regulator_hot_gpio_support = 1; > > + data->registry_data.didt_support = 1; > + if (data->registry_data.didt_support) { > + data->registry_data.didt_mode = 6; > + data->registry_data.sq_ramping_support = 1; > + data->registry_data.db_ramping_support = 0; > + data->registry_data.td_ramping_support = 0; > + data->registry_data.tcp_ramping_support = 0; > + data->registry_data.dbr_ramping_support = 0; > + data->registry_data.edc_didt_support = 1; > + data->registry_data.gc_didt_support = 0; > + data->registry_data.psm_didt_support = 0; > + } > + > data->display_voltage_mode = > PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; > data->dcef_clk_quad_eqn_a = > PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; > data->dcef_clk_quad_eqn_b = > PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; > @@ -222,6 +235,8 @@ static int vega10_set_features_platform_caps(struct > pp_hwmgr *hwmgr) > phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_PowerContainment); > phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_DiDtSupport); > + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_SQRamping); > phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_DBRamping); > @@ -229,6 +244,34 @@ static int vega10_set_features_platform_caps(struct > pp_hwmgr *hwmgr) > PHM_PlatformCaps_TDRamping); > phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_TCPRamping); > + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_DBRRamping); > + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_DiDtEDCEnable); > + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_GCEDC); > + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_PSM); > + > + if (data->registry_data.didt_support) { > + phm_cap_set(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_DiDtSupport); > + if (data->registry_data.sq_ramping_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); > + if (data->registry_data.db_ramping_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); > + if (data->registry_data.td_ramping_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); > + if (data->registry_data.tcp_ramping_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); > + if (data->registry_data.dbr_ramping_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); > + if (data->registry_data.edc_didt_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); > + if (data->registry_data.gc_didt_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); > + if (data->registry_data.psm_didt_support) > + phm_cap_set(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); > + } > > if (data->registry_data.power_containment_support) > phm_cap_set(hwmgr->platform_descriptor.platformCaps, > @@ -321,6 +364,7 @@ static void vega10_init_dpm_defaults(struct > pp_hwmgr *hwmgr) > data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = > FEATURE_FAN_CONTROL_BIT; > data->smu_features[GNLD_ACG].smu_feature_id = > FEATURE_ACG_BIT; > + data->smu_features[GNLD_DIDT].smu_feature_id = > FEATURE_GFX_EDC_BIT; > > if (!data->registry_data.prefetcher_dpm_key_disabled) > data->smu_features[GNLD_DPM_PREFETCHER].supported = > true; > @@ -390,6 +434,9 @@ static void vega10_init_dpm_defaults(struct > pp_hwmgr *hwmgr) > if ((data->smu_version & 0xff000000) == 0x5000000) > data->smu_features[GNLD_ACG].supported = true; > > + if (data->registry_data.didt_support) > + data->smu_features[GNLD_DIDT].supported = true; > + > } > > #ifdef PPLIB_VEGA10_EVV_SUPPORT > @@ -2906,6 +2953,11 @@ static int vega10_enable_dpm_tasks(struct > pp_hwmgr *hwmgr) > PP_ASSERT_WITH_CODE(!tmp_result, > "Failed to start DPM!", result = tmp_result); > > + /* enable didt, do not abort if failed didt */ > + tmp_result = vega10_enable_didt_config(hwmgr); > + PP_ASSERT(!tmp_result, > + "Failed to enable didt config!"); > + > tmp_result = vega10_enable_power_containment(hwmgr); > PP_ASSERT_WITH_CODE(!tmp_result, > "Failed to enable power containment!", > @@ -4735,6 +4787,10 @@ static int vega10_disable_dpm_tasks(struct > pp_hwmgr *hwmgr) > PP_ASSERT_WITH_CODE((tmp_result == 0), > "Failed to disable power containment!", result = > tmp_result); > > + tmp_result = vega10_disable_didt_config(hwmgr); > + PP_ASSERT_WITH_CODE((tmp_result == 0), > + "Failed to disable didt config!", result = tmp_result); > + > tmp_result = vega10_avfs_enable(hwmgr, false); > PP_ASSERT_WITH_CODE((tmp_result == 0), > "Failed to disable AVFS!", result = tmp_result); > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > index 4150801..5c97a8b 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h > @@ -232,7 +232,9 @@ struct vega10_registry_data { > uint8_t cac_support; > uint8_t clock_stretcher_support; > uint8_t db_ramping_support; > + uint8_t didt_mode; > uint8_t didt_support; > + uint8_t edc_didt_support; > uint8_t dynamic_state_patching_support; > uint8_t enable_pkg_pwr_tracking_feature; > uint8_t enable_tdc_limit_feature; > @@ -265,6 +267,9 @@ struct vega10_registry_data { > uint8_t tcp_ramping_support; > uint8_t tdc_support; > uint8_t td_ramping_support; > + uint8_t dbr_ramping_support; > + uint8_t gc_didt_support; > + uint8_t psm_didt_support; > uint8_t thermal_out_gpio_support; > uint8_t thermal_support; > uint8_t fw_ctf_enabled; > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > index 3f72268..22334a1 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > @@ -26,7 +26,1298 @@ > #include "vega10_powertune.h" > #include "vega10_smumgr.h" > #include "vega10_ppsmc.h" > +#include "vega10_inc.h" > #include "pp_debug.h" > +#include "pp_soc15.h" > + > +static const struct vega10_didt_config_reg > SEDiDtTuningCtrlConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ */ > + { ixDIDT_SQ_TUNING_CTRL, > DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, > DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 }, > + { ixDIDT_SQ_TUNING_CTRL, > DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, > DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 }, > + > + /* DIDT_TD */ > + { ixDIDT_TD_TUNING_CTRL, > DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, > DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde }, > + { ixDIDT_TD_TUNING_CTRL, > DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, > DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde }, > + > + /* DIDT_TCP */ > + { ixDIDT_TCP_TUNING_CTRL, > DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, > DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, > + { ixDIDT_TCP_TUNING_CTRL, > DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, > DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, > + > + /* DIDT_DB */ > + { ixDIDT_DB_TUNING_CTRL, > DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, > DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, > + { ixDIDT_DB_TUNING_CTRL, > DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, > DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /*DIDT_SQ_CTRL3 */ > + { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, > DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, > DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 > }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, > DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 > }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, > DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, > DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, > DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, > DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, > DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL3, > DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, > DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, > + > + /*DIDT_TCP_CTRL3 */ > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, > DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, > DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 > }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, > DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 > }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, > DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, > DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, > DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, > DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, > DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL3, > DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, > DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, > + > + /*DIDT_TD_CTRL3 */ > + { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, > DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, > DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 > }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, > DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 > }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, > DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, > DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, > DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, > DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, > DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL3, > DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, > DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, > + > + /*DIDT_DB_CTRL3 */ > + { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, > DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, > DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 > }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, > DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 > }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, > DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, > DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, > DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, > DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, > DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL3, > DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, > DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ */ > + { ixDIDT_SQ_CTRL2, > DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, > DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 }, > + { ixDIDT_SQ_CTRL2, > DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, > DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, > + { ixDIDT_SQ_CTRL2, > DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, > DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 }, > + > + /* DIDT_TD */ > + { ixDIDT_TD_CTRL2, > DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, > DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff }, > + { ixDIDT_TD_CTRL2, > DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, > DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, > + { ixDIDT_TD_CTRL2, > DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, > DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, > + > + /* DIDT_TCP */ > + { ixDIDT_TCP_CTRL2, > DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, > DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, > + { ixDIDT_TCP_CTRL2, > DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, > DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, > + { ixDIDT_TCP_CTRL2, > DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, > DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, > + > + /* DIDT_DB */ > + { ixDIDT_DB_CTRL2, > DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, > DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, > + { ixDIDT_DB_CTRL2, > DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, > DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, > + { ixDIDT_DB_CTRL2, > DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, > DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ */ > + { ixDIDT_SQ_CTRL1, > DIDT_SQ_CTRL1__MIN_POWER_MASK, > DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL1, > DIDT_SQ_CTRL1__MAX_POWER_MASK, > DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff }, > + /* DIDT_TD */ > + { ixDIDT_TD_CTRL1, > DIDT_TD_CTRL1__MIN_POWER_MASK, > DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL1, > DIDT_TD_CTRL1__MAX_POWER_MASK, > DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff }, > + /* DIDT_TCP */ > + { ixDIDT_TCP_CTRL1, > DIDT_TCP_CTRL1__MIN_POWER_MASK, > DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL1, > DIDT_TCP_CTRL1__MAX_POWER_MASK, > DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff }, > + /* DIDT_DB */ > + { ixDIDT_DB_CTRL1, > DIDT_DB_CTRL1__MIN_POWER_MASK, > DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL1, > DIDT_DB_CTRL1__MAX_POWER_MASK, > DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > + > +static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ */ > + { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, > 0x2B363B1A }, > + { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, > 0x270B2432 }, > + { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, > 0, 0x00000018 }, > + > + /* DIDT_TD */ > + { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, > 0x2B1D220F }, > + { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, > 0x00007558 }, > + { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, > 0, 0x00000000 }, > + > + /* DIDT_TCP */ > + { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, > 0, 0x5ACE160D }, > + { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, > 0, 0x00000000 }, > + > + /* DIDT_DB */ > + { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, > 0x0E152A0F }, > + { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, > 0x09061813 }, > + { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, > 0, 0x00000013 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ */ > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, > DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, > DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, > DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, > DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, > DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, > DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, > DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, > DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, > DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_CTRL0, > DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, > DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, > + /* DIDT_TD */ > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, > DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__PHASE_OFFSET_MASK, > DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, > DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, > DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, > DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, > DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, > DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, > DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, > DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_CTRL0, > DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, > DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, > + /* DIDT_TCP */ > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, > DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, > DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, > DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, > DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, > DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, > DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, > DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, > DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, > DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, > + { ixDIDT_TCP_CTRL0, > DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, > DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, > + /* DIDT_DB */ > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, > DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__PHASE_OFFSET_MASK, > DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, > DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, > DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, > DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, > DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, > DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, > DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, > DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, > DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, > + { ixDIDT_DB_CTRL0, > DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, > DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > + > +static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ */ > + { ixDIDT_SQ_STALL_CTRL, > DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, > DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, > + { ixDIDT_SQ_STALL_CTRL, > DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, > DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, > + { ixDIDT_SQ_STALL_CTRL, > DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, > DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a > }, > + { ixDIDT_SQ_STALL_CTRL, > DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, > DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a > }, > + > + /* DIDT_TD */ > + { ixDIDT_TD_STALL_CTRL, > DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, > DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, > + { ixDIDT_TD_STALL_CTRL, > DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, > DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, > + { ixDIDT_TD_STALL_CTRL, > DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, > DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a > }, > + { ixDIDT_TD_STALL_CTRL, > DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, > DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a > }, > + > + /* DIDT_TCP */ > + { ixDIDT_TCP_STALL_CTRL, > DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, > DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, > + { ixDIDT_TCP_STALL_CTRL, > DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, > DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, > + { ixDIDT_TCP_STALL_CTRL, > DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, > DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a > }, > + { ixDIDT_TCP_STALL_CTRL, > DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, > DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, > 0x000a }, > + > + /* DIDT_DB */ > + { ixDIDT_DB_STALL_CTRL, > DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, > DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, > + { ixDIDT_DB_STALL_CTRL, > DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, > DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, > + { ixDIDT_DB_STALL_CTRL, > DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, > DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a > }, > + { ixDIDT_DB_STALL_CTRL, > DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, > DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a > }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > SEDiDtStallPatternConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* DIDT_SQ_STALL_PATTERN_1_2 */ > + { ixDIDT_SQ_STALL_PATTERN_1_2, > DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, > DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 > }, > + { ixDIDT_SQ_STALL_PATTERN_1_2, > DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, > DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 > }, > + > + /* DIDT_SQ_STALL_PATTERN_3_4 */ > + { ixDIDT_SQ_STALL_PATTERN_3_4, > DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, > DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 > }, > + { ixDIDT_SQ_STALL_PATTERN_3_4, > DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, > DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 > }, > + > + /* DIDT_SQ_STALL_PATTERN_5_6 */ > + { ixDIDT_SQ_STALL_PATTERN_5_6, > DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, > DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 > }, > + { ixDIDT_SQ_STALL_PATTERN_5_6, > DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, > DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 > }, > + > + /* DIDT_SQ_STALL_PATTERN_7 */ > + { ixDIDT_SQ_STALL_PATTERN_7, > DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, > DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, > + > + /* DIDT_TCP_STALL_PATTERN_1_2 */ > + { ixDIDT_TCP_STALL_PATTERN_1_2, > DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, > DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 > }, > + { ixDIDT_TCP_STALL_PATTERN_1_2, > DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, > DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 > }, > + > + /* DIDT_TCP_STALL_PATTERN_3_4 */ > + { ixDIDT_TCP_STALL_PATTERN_3_4, > DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, > DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 > }, > + { ixDIDT_TCP_STALL_PATTERN_3_4, > DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, > DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 > }, > + > + /* DIDT_TCP_STALL_PATTERN_5_6 */ > + { ixDIDT_TCP_STALL_PATTERN_5_6, > DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, > DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 > }, > + { ixDIDT_TCP_STALL_PATTERN_5_6, > DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, > DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 > }, > + > + /* DIDT_TCP_STALL_PATTERN_7 */ > + { ixDIDT_TCP_STALL_PATTERN_7, > DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, > DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, > + > + /* DIDT_TD_STALL_PATTERN_1_2 */ > + { ixDIDT_TD_STALL_PATTERN_1_2, > DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, > DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 > }, > + { ixDIDT_TD_STALL_PATTERN_1_2, > DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, > DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 > }, > + > + /* DIDT_TD_STALL_PATTERN_3_4 */ > + { ixDIDT_TD_STALL_PATTERN_3_4, > DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, > DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 > }, > + { ixDIDT_TD_STALL_PATTERN_3_4, > DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, > DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 > }, > + > + /* DIDT_TD_STALL_PATTERN_5_6 */ > + { ixDIDT_TD_STALL_PATTERN_5_6, > DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, > DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 > }, > + { ixDIDT_TD_STALL_PATTERN_5_6, > DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, > DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 > }, > + > + /* DIDT_TD_STALL_PATTERN_7 */ > + { ixDIDT_TD_STALL_PATTERN_7, > DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, > DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, > + > + /* DIDT_DB_STALL_PATTERN_1_2 */ > + { ixDIDT_DB_STALL_PATTERN_1_2, > DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, > DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 > }, > + { ixDIDT_DB_STALL_PATTERN_1_2, > DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, > DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 > }, > + > + /* DIDT_DB_STALL_PATTERN_3_4 */ > + { ixDIDT_DB_STALL_PATTERN_3_4, > DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, > DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 > }, > + { ixDIDT_DB_STALL_PATTERN_3_4, > DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, > DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 > }, > + > + /* DIDT_DB_STALL_PATTERN_5_6 */ > + { ixDIDT_DB_STALL_PATTERN_5_6, > DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, > DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 > }, > + { ixDIDT_DB_STALL_PATTERN_5_6, > DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, > DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 > }, > + > + /* DIDT_DB_STALL_PATTERN_7 */ > + { ixDIDT_DB_STALL_PATTERN_7, > DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, > DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x00060021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x00860021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x01060021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x01860021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x02060021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x02860021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x03060021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x03860021 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x04060021 }, > + /* TD */ > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x000E0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x008E0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x010E0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x018E0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x020E0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x028E0020 }, > + /* TCP */ > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x001c0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x009c0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x011c0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x019c0020 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x021c0020 }, > + /* DB */ > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x00200008 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x00820008 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x01020008 }, > + { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, > 0x01820008 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > + > +static const struct vega10_didt_config_reg > SEEDCStallPatternConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, > 0, 0x00030001 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, > 0, 0x000F0007 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, > 0, 0x003F001F }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, > 0, 0x0000007F }, > + /* TD */ > + { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, > 0, 0x00000000 }, > + /* TCP */ > + { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, > 0, 0x00000000 }, > + /* DB */ > + { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, > 0, 0x00000000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > SEEDCForceStallPatternConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, > 0, 0x00000015 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, > 0, 0x00000000 }, > + /* TD */ > + { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, > 0, 0x00000015 }, > + { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, > 0, 0x00000000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] > = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + /* TD */ > + { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + /* TCP */ > + { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, > 0, 0x00000000 }, > + { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, > 0, 0x00000000 }, > + /* DB */ > + { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, > 0, 0x00000000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] > = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, > 0, 0x0000010E }, > + { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, > 0, 0xFFFFFFFF }, > + { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, > 0, 0xFFFFFFFF }, > + { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, > 0, 0xFFFFFFFF }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] > = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, > DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, > DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > SEEDCCtrlForceStallConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ */ > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, > DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, > + > + /* TD */ > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_EN_MASK, > DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, > DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, > DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, > DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, > DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, > DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_TD_EDC_CTRL, > DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, > DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > GCDiDtDroopCtrlConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { mmGC_DIDT_DROOP_CTRL, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 }, > + { mmGC_DIDT_DROOP_CTRL, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 }, > + { mmGC_DIDT_DROOP_CTRL, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 }, > + { mmGC_DIDT_DROOP_CTRL, > GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, > GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 }, > + { mmGC_DIDT_DROOP_CTRL, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, > GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 > }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { mmGC_DIDT_CTRL0, > GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, > GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, > + { mmGC_DIDT_CTRL0, > GC_DIDT_CTRL0__PHASE_OFFSET_MASK, > GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, > + { mmGC_DIDT_CTRL0, > GC_DIDT_CTRL0__DIDT_SW_RST_MASK, > GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 }, > + { mmGC_DIDT_CTRL0, > GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, > GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { mmGC_DIDT_CTRL0, > GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, > GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, > + { 0xFFFFFFFF } /* End of list */ > +}; > + > + > +static const struct vega10_didt_config_reg > PSMSEEDCStallPatternConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ EDC STALL PATTERNs */ > + { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, > DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, > DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, > 0x0101 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, > DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, > DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, > 0x0101 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, > DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, > DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, > 0x1111 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, > DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, > DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, > 0x1111 }, > + > + { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, > DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, > DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, > 0x1515 }, > + { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, > DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, > DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, > 0x1515 }, > + > + { ixDIDT_SQ_EDC_STALL_PATTERN_7, > DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, > DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, > 0x5555 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > PSMSEEDCStallDelayConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ EDC STALL DELAYs */ > + { ixDIDT_SQ_EDC_STALL_DELAY_1, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_1, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_1, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_1, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, > DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 }, > + > + { ixDIDT_SQ_EDC_STALL_DELAY_2, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_2, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_2, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_2, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, > DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 }, > + > + { ixDIDT_SQ_EDC_STALL_DELAY_3, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_3, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_3, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_3, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, > DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 }, > + > + { ixDIDT_SQ_EDC_STALL_DELAY_4, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_4, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_4, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_STALL_DELAY_4, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, > DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > PSMSEEDCThresholdConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ EDC THRESHOLD */ > + { ixDIDT_SQ_EDC_THRESHOLD, > DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK, > DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > PSMSEEDCCtrlResetConfig_Vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ EDC CTRL */ > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, > DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] > = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + /* SQ EDC CTRL */ > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, > DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, > DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, > DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, > + { ixDIDT_SQ_EDC_CTRL, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, > DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > PSMGCEDCThresholdConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { mmGC_EDC_THRESHOLD, > GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK, > GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > PSMGCEDCDroopCtrlConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { mmGC_EDC_DROOP_CTRL, > GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, > GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 }, > + { mmGC_EDC_DROOP_CTRL, > GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, > GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 }, > + { mmGC_EDC_DROOP_CTRL, > GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, > GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 }, > + { mmGC_EDC_DROOP_CTRL, > GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, > GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 }, > + { mmGC_EDC_DROOP_CTRL, > GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, > GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > PSMGCEDCCtrlResetConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, > GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_SW_RST_MASK, > GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_FORCE_STALL_MASK, > GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] > = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, > GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_SW_RST_MASK, > GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, > GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_FORCE_STALL_MASK, > GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, > GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, > + { mmGC_EDC_CTRL, > GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, > GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg > AvfsPSMResetConfig_vega10[]= > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { 0x16A02, 0xFFFFFFFF, 0x0, > 0x0000005F }, > + { 0x16A05, 0xFFFFFFFF, 0x0, > 0x00000001 }, > + { 0x16A06, 0x00000001, 0x0, > 0x02000000 }, > + { 0x16A01, 0xFFFFFFFF, 0x0, > 0x00003027 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = > +{ > +/* ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + * Offset Mask Shift > Value > + * ----------------------------------------------------------------------------------------- > ---------------------------------------------------------------------------------------- > + */ > + { 0x16A05, 0xFFFFFFFF, 0x18, > 0x00000001 }, > + { 0x16A05, 0xFFFFFFFF, 0x8, > 0x00000003 }, > + { 0x16A05, 0xFFFFFFFF, 0xa, > 0x00000006 }, > + { 0x16A05, 0xFFFFFFFF, 0x7, > 0x00000000 }, > + { 0x16A06, 0xFFFFFFFF, 0x18, > 0x00000001 }, > + { 0x16A06, 0xFFFFFFFF, 0x19, > 0x00000001 }, > + { 0x16A01, 0xFFFFFFFF, 0x0, > 0x00003027 }, > + > + { 0xFFFFFFFF } /* End of list */ > +}; > + > +static int vega10_program_didt_config_registers(struct pp_hwmgr > *hwmgr, const struct vega10_didt_config_reg *config_regs, enum > vega10_didt_config_reg_type reg_type) > +{ > + uint32_t data; > + > + PP_ASSERT_WITH_CODE((config_regs != NULL), > "[vega10_program_didt_config_registers] Invalid config register table!", > return -EINVAL); > + > + while (config_regs->offset != 0xFFFFFFFF) { > + switch (reg_type) { > + case VEGA10_CONFIGREG_DIDT: > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, config_regs->offset); > + data &= ~config_regs->mask; > + data |= ((config_regs->value << config_regs->shift) & > config_regs->mask); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, config_regs->offset, data); > + break; > + case VEGA10_CONFIGREG_GCCAC: > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG_GC_CAC, config_regs->offset); > + data &= ~config_regs->mask; > + data |= ((config_regs->value << config_regs->shift) & > config_regs->mask); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG_GC_CAC, config_regs->offset, data); > + break; > + case VEGA10_CONFIGREG_SECAC: > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG_SE_CAC, config_regs->offset); > + data &= ~config_regs->mask; > + data |= ((config_regs->value << config_regs->shift) & > config_regs->mask); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG_SE_CAC, config_regs->offset, data); > + break; > + default: > + return -EINVAL; > + } > + > + config_regs++; > + } > + > + return 0; > +} > + > +static int vega10_program_gc_didt_config_registers(struct pp_hwmgr > *hwmgr, const struct vega10_didt_config_reg *config_regs) > +{ > + uint32_t data; > + > + while (config_regs->offset != 0xFFFFFFFF) { > + data = cgs_read_register(hwmgr->device, config_regs- > >offset); > + data &= ~config_regs->mask; > + data |= ((config_regs->value << config_regs->shift) & > config_regs->mask); > + cgs_write_register(hwmgr->device, config_regs->offset, > data); > + config_regs++; > + } > + > + return 0; > +} > + > +static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool > enable) > +{ > + uint32_t data; > + int result; > + uint32_t en = (enable ? 1 : 0); > + uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | > TD_PCC_MASK; > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_SQRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0); > + data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; > + data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data); > + didt_block_info &= ~SQ_Enable_MASK; > + didt_block_info |= en << SQ_Enable_SHIFT; > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_DBRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0); > + data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; > + data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data); > + didt_block_info &= ~DB_Enable_MASK; > + didt_block_info |= en << DB_Enable_SHIFT; > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_TDRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0); > + data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; > + data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & > DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data); > + didt_block_info &= ~TD_Enable_MASK; > + didt_block_info |= en << TD_Enable_SHIFT; > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_TCPRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0); > + data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; > + data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) > & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data); > + didt_block_info &= ~TCP_Enable_MASK; > + didt_block_info |= en << TCP_Enable_SHIFT; > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_DBRRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0); > + data &= ~DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK; > + data |= ((en << DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT) > & DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0, data); > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_DiDtEDCEnable)) { > + if (phm_cap_enabled(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); > + data &= ~DIDT_SQ_EDC_CTRL__EDC_EN_MASK; > + data |= ((en << > DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT) & > DIDT_SQ_EDC_CTRL__EDC_EN_MASK); > + data &= > ~DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK; > + data |= ((~en << > DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT) & > DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); > + } > + > + if (phm_cap_enabled(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); > + data &= ~DIDT_DB_EDC_CTRL__EDC_EN_MASK; > + data |= ((en << > DIDT_DB_EDC_CTRL__EDC_EN__SHIFT) & > DIDT_DB_EDC_CTRL__EDC_EN_MASK); > + data &= > ~DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK; > + data |= ((~en << > DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT) & > DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); > + } > + > + if (phm_cap_enabled(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); > + data &= ~DIDT_TD_EDC_CTRL__EDC_EN_MASK; > + data |= ((en << > DIDT_TD_EDC_CTRL__EDC_EN__SHIFT) & > DIDT_TD_EDC_CTRL__EDC_EN_MASK); > + data &= > ~DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK; > + data |= ((~en << > DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT) & > DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); > + } > + > + if (phm_cap_enabled(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); > + data &= ~DIDT_TCP_EDC_CTRL__EDC_EN_MASK; > + data |= ((en << > DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT) & > DIDT_TCP_EDC_CTRL__EDC_EN_MASK); > + data &= > ~DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK; > + data |= ((~en << > DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT) & > DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); > + } > + > + if (phm_cap_enabled(hwmgr- > >platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { > + data = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); > + data &= ~DIDT_DBR_EDC_CTRL__EDC_EN_MASK; > + data |= ((en << > DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT) & > DIDT_DBR_EDC_CTRL__EDC_EN_MASK); > + data &= > ~DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK; > + data |= ((~en << > DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT) & > DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK); > + cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); > + } > + } > + > + if (enable) { > + /* For Vega10, SMC does not support any mask yet. */ > + result = smum_send_msg_to_smc_with_parameter(hwmgr- > >smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); > + PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure > Gfx Didt Failed!"); > + } > +} > + > +static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr > *hwmgr) > +{ > + int result; > + uint32_t num_se, count, data; > + struct cgs_system_info sys_info = {0}; > + uint32_t reg; > + > + sys_info.size = sizeof(struct cgs_system_info); > + sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; > + if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) > + num_se = sys_info.value; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + cgs_lock_grbm_idx(hwmgr->device, true); > + reg = soc15_get_register_offset(GC_HWID, 0, > mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); > + for (count = 0; count < num_se; count++) { > + data = > GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | > GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << > GRBM_GFX_INDEX__SE_INDEX__SHIFT); > + cgs_write_register(hwmgr->device, reg, data); > + > + result = vega10_program_didt_config_registers(hwmgr, > SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); > + > + if (0 != result) > + break; > + } > + cgs_write_register(hwmgr->device, reg, 0xE0000000); > + cgs_lock_grbm_idx(hwmgr->device, false); > + > + vega10_didt_set_mask(hwmgr, true); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + return 0; > +} > + > +static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr > *hwmgr) > +{ > + cgs_enter_safe_mode(hwmgr->device, true); > + > + vega10_didt_set_mask(hwmgr, false); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + return 0; > +} > + > +static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) > +{ > + int result; > + uint32_t num_se, count, data; > + struct cgs_system_info sys_info = {0}; > + uint32_t reg; > + > + sys_info.size = sizeof(struct cgs_system_info); > + sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; > + if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) > + num_se = sys_info.value; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + cgs_lock_grbm_idx(hwmgr->device, true); > + reg = soc15_get_register_offset(GC_HWID, 0, > mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); > + for (count = 0; count < num_se; count++) { > + data = > GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | > GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << > GRBM_GFX_INDEX__SE_INDEX__SHIFT); > + cgs_write_register(hwmgr->device, reg, data); > + > + result = vega10_program_didt_config_registers(hwmgr, > SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); > + if (0 != result) > + break; > + } > + cgs_write_register(hwmgr->device, reg, 0xE0000000); > + cgs_lock_grbm_idx(hwmgr->device, false); > + > + vega10_didt_set_mask(hwmgr, true); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + vega10_program_gc_didt_config_registers(hwmgr, > GCDiDtDroopCtrlConfig_vega10); > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_GCEDC)) > + vega10_program_gc_didt_config_registers(hwmgr, > GCDiDtCtrl0Config_vega10); > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_PSM)) > + vega10_program_gc_didt_config_registers(hwmgr, > AvfsPSMInitConfig_vega10); > + > + return 0; > +} > + > +static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) > +{ > + uint32_t data; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + vega10_didt_set_mask(hwmgr, false); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_GCEDC)) { > + data = 0x00000000; > + cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, > data); > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_PSM)) > + vega10_program_gc_didt_config_registers(hwmgr, > AvfsPSMResetConfig_vega10); > + > + return 0; > +} > + > +static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) > +{ > + int result; > + uint32_t num_se, count, data; > + struct cgs_system_info sys_info = {0}; > + uint32_t reg; > + > + sys_info.size = sizeof(struct cgs_system_info); > + sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; > + if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) > + num_se = sys_info.value; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + cgs_lock_grbm_idx(hwmgr->device, true); > + reg = soc15_get_register_offset(GC_HWID, 0, > mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); > + for (count = 0; count < num_se; count++) { > + data = > GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | > GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << > GRBM_GFX_INDEX__SE_INDEX__SHIFT); > + cgs_write_register(hwmgr->device, reg, data); > + result = vega10_program_didt_config_registers(hwmgr, > SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + > + if (0 != result) > + break; > + } > + cgs_write_register(hwmgr->device, reg, 0xE0000000); > + cgs_lock_grbm_idx(hwmgr->device, false); > + > + vega10_didt_set_mask(hwmgr, true); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + return 0; > +} > + > +static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr) > +{ > + cgs_enter_safe_mode(hwmgr->device, true); > + > + vega10_didt_set_mask(hwmgr, false); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + return 0; > +} > + > +static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) > +{ > + int result; > + uint32_t num_se; > + uint32_t count, data; > + struct cgs_system_info sys_info = {0}; > + uint32_t reg; > + > + sys_info.size = sizeof(struct cgs_system_info); > + sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; > + if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) > + num_se = sys_info.value; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + vega10_program_gc_didt_config_registers(hwmgr, > AvfsPSMResetConfig_vega10); > + > + cgs_lock_grbm_idx(hwmgr->device, true); > + reg = soc15_get_register_offset(GC_HWID, 0, > mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); > + for (count = 0; count < num_se; count++) { > + data = > GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | > GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << > GRBM_GFX_INDEX__SE_INDEX__SHIFT); > + cgs_write_register(hwmgr->device, reg, data); > + result |= vega10_program_didt_config_registers(hwmgr, > PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + > + if (0 != result) > + break; > + } > + cgs_write_register(hwmgr->device, reg, 0xE0000000); > + cgs_lock_grbm_idx(hwmgr->device, false); > + > + vega10_didt_set_mask(hwmgr, true); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + vega10_program_gc_didt_config_registers(hwmgr, > PSMGCEDCDroopCtrlConfig_vega10); > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_GCEDC)) { > + vega10_program_gc_didt_config_registers(hwmgr, > PSMGCEDCCtrlResetConfig_vega10); > + vega10_program_gc_didt_config_registers(hwmgr, > PSMGCEDCCtrlConfig_vega10); > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_PSM)) > + vega10_program_gc_didt_config_registers(hwmgr, > AvfsPSMInitConfig_vega10); > + > + return 0; > +} > + > +static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) > +{ > + uint32_t data; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + vega10_didt_set_mask(hwmgr, false); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_GCEDC)) { > + data = 0x00000000; > + cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, > data); > + } > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > PHM_PlatformCaps_PSM)) > + vega10_program_gc_didt_config_registers(hwmgr, > AvfsPSMResetConfig_vega10); > + > + return 0; > +} > + > +static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr > *hwmgr) > +{ > + uint32_t reg; > + int result; > + > + cgs_enter_safe_mode(hwmgr->device, true); > + > + cgs_lock_grbm_idx(hwmgr->device, true); > + reg = soc15_get_register_offset(GC_HWID, 0, > mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); > + cgs_write_register(hwmgr->device, reg, 0xE0000000); > + cgs_lock_grbm_idx(hwmgr->device, false); > + > + result = vega10_program_didt_config_registers(hwmgr, > SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + result |= vega10_program_didt_config_registers(hwmgr, > SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT); > + if (0 != result) > + return result; > + > + vega10_didt_set_mask(hwmgr, true); > + > + cgs_enter_safe_mode(hwmgr->device, false); > + > + return 0; > +} > + > +static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr > *hwmgr) > +{ > + int result; > + > + result = vega10_disable_se_edc_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT > disable clock gating failed!", return result); > + > + return 0; > +} > + > +int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) > +{ > + int result = 0; > + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr- > >backend); > + > + if (data->smu_features[GNLD_DIDT].supported) { > + if (data->smu_features[GNLD_DIDT].enabled) > + PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt > Already enabled!\n"); > + > + switch (data->registry_data.didt_mode) { > + case 0: > + result = > vega10_enable_cac_driving_se_didt_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] > Attempt to enable DiDt Mode 0 Failed!", return result); > + break; > + case 2: > + result = > vega10_enable_psm_gc_didt_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] > Attempt to enable DiDt Mode 2 Failed!", return result); > + break; > + case 3: > + result = vega10_enable_se_edc_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] > Attempt to enable DiDt Mode 3 Failed!", return result); > + break; > + case 1: > + case 4: > + case 5: > + result = > vega10_enable_psm_gc_edc_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] > Attempt to enable DiDt Mode 5 Failed!", return result); > + break; > + case 6: > + result = > vega10_enable_se_edc_force_stall_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] > Attempt to enable DiDt Mode 6 Failed!", return result); > + break; > + default: > + result = -EINVAL; > + break; > + } > + > + if (0 == result) { > + > PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr- > >smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), > + "[EnableDiDtConfig] Attempt to Enable DiDt > feature Failed!", return result); > + data->smu_features[GNLD_DIDT].enabled = true; > + } > + } > + > + return result; > +} > + > +int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) > +{ > + int result = 0; > + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr- > >backend); > + > + if (data->smu_features[GNLD_DIDT].supported) { > + if (!data->smu_features[GNLD_DIDT].enabled) > + PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt > Already Disabled!\n"); > + > + switch (data->registry_data.didt_mode) { > + case 0: > + result = > vega10_disable_cac_driving_se_didt_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] > Attempt to disable DiDt Mode 0 Failed!", return result); > + break; > + case 2: > + result = > vega10_disable_psm_gc_didt_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] > Attempt to disable DiDt Mode 2 Failed!", return result); > + break; > + case 3: > + result = vega10_disable_se_edc_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] > Attempt to disable DiDt Mode 3 Failed!", return result); > + break; > + case 1: > + case 4: > + case 5: > + result = > vega10_disable_psm_gc_edc_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] > Attempt to disable DiDt Mode 5 Failed!", return result); > + break; > + case 6: > + result = > vega10_disable_se_edc_force_stall_config(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] > Attempt to disable DiDt Mode 6 Failed!", return result); > + break; > + default: > + result = -EINVAL; > + break; > + } > + > + if (0 == result) { > + PP_ASSERT_WITH_CODE((0 != > vega10_enable_smc_features(hwmgr->smumgr, false, data- > >smu_features[GNLD_DIDT].smu_feature_bitmap)), > + "[DisableDiDtConfig] Attempt to > Disable DiDt feature Failed!", return result); > + data->smu_features[GNLD_DIDT].enabled = false; > + } > + } > + > + return result; > +} > > void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) > { > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > index 9ecaa27..b95771a 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > @@ -31,6 +31,12 @@ enum vega10_pt_config_reg_type { > VEGA10_CONFIGREG_MAX > }; > > +enum vega10_didt_config_reg_type { > + VEGA10_CONFIGREG_DIDT = 0, > + VEGA10_CONFIGREG_GCCAC, > + VEGA10_CONFIGREG_SECAC > +}; > + > /* PowerContainment Features */ > #define POWERCONTAINMENT_FEATURE_DTE 0x00000001 > #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 > @@ -44,6 +50,13 @@ struct vega10_pt_config_reg { > enum vega10_pt_config_reg_type type; > }; > > +struct vega10_didt_config_reg { > + uint32_t offset; > + uint32_t mask; > + uint32_t shift; > + uint32_t value; > +}; > + > struct vega10_pt_defaults { > uint8_t SviLoadLineEn; > uint8_t SviLoadLineVddC; > @@ -62,5 +75,8 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, > uint32_t n); > int vega10_power_control_set_level(struct pp_hwmgr *hwmgr); > int vega10_disable_power_containment(struct pp_hwmgr *hwmgr); > > +int vega10_enable_didt_config(struct pp_hwmgr *hwmgr); > +int vega10_disable_didt_config(struct pp_hwmgr *hwmgr); > + > #endif /* _VEGA10_POWERTUNE_H_ */ > > diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h > b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h > index a1ebe10..a4c8b09 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h > @@ -164,9 +164,14 @@ enum phm_platform_caps { > PHM_PlatformCaps_EnablePlatformPowerManagement, /* > indicates that Platform Power Management feature is supported */ > PHM_PlatformCaps_SurpriseRemoval, /* indicates that > surprise removal feature is requested */ > PHM_PlatformCaps_NewCACVoltage, /* indicates new > CAC voltage table support */ > + PHM_PlatformCaps_DiDtSupport, /* for dI/dT feature > */ > PHM_PlatformCaps_DBRamping, /* for dI/dT feature > */ > PHM_PlatformCaps_TDRamping, /* for dI/dT feature > */ > PHM_PlatformCaps_TCPRamping, /* for dI/dT feature > */ > + PHM_PlatformCaps_DBRRamping, /* for dI/dT feature > */ > + PHM_PlatformCaps_DiDtEDCEnable, /* for dI/dT feature > */ > + PHM_PlatformCaps_GCEDC, /* for dI/dT feature */ > + PHM_PlatformCaps_PSM, /* for dI/dT feature */ > PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC > will manage thermal events */ > PHM_PlatformCaps_FPS, /* FPS support */ > PHM_PlatformCaps_ACP, /* ACP support */ > diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h > b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h > index f3f9ebb..822cd8b 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h > @@ -42,6 +42,12 @@ > } \ > } while (0) > > +#define PP_ASSERT(cond, msg) \ > + do { \ > + if (!(cond)) { \ > + pr_warn("%s\n", msg); \ > + } \ > + } while (0) > > #define PP_DBG_LOG(fmt, ...) \ > do { \ > diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h > b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h > index 227d999..a511611 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h > @@ -41,6 +41,8 @@ inline static uint32_t soc15_get_register_offset( > reg = MP1_BASE.instance[inst].segment[segment] + offset; > else if (hw_id == DF_HWID) > reg = DF_BASE.instance[inst].segment[segment] + offset; > + else if (hw_id == GC_HWID) > + reg = GC_BASE.instance[inst].segment[segment] + offset; > > return reg; > } > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
