Am 06.07.2017 um 19:46 schrieb Alex Deucher:
> Used for nbio registers that need to be initialized. Currently
> only used for a golden setting that got missed on some boards.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com> for the series.
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 13 +++++++++++++
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 1 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 61c0028..045988b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -32,6 +32,7 @@
>
> #define smnCPM_CONTROL 0x11180460
> #define smnPCIE_CNTL2 0x11180070
> +#define smnPCIE_CONFIG_CNTL 0x11180044
>
> u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
> {
> @@ -256,3 +257,15 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
> adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
> }
> }
> +
> +void nbio_v6_1_init_registers(struct amdgpu_device *adev)
> +{
> + uint32_t def, data;
> +
> + def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
> + data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> + data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
> +
> + if (def != data)
> + WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> index f6f8bc0..686e4b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> @@ -50,5 +50,6 @@ void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool
> void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable);
> void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
> void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);
> +void nbio_v6_1_init_registers(struct amdgpu_device *adev);
>
> #endif
