> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Thursday, January 26, 2017 6:01 AM > To: amd-gfx at lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 12/12] drm/amdgpu: refine vce3.0 code and related > powerplay pg code. > > 1. not start vce3.0 when hw_init > 2. stop vce3.0 when vce idle. > 3. pg mask used to ctrl power down/up vce. > 4. change cg pg sequence in powerplay. > > Change-Id: I852c4cf7066153074a12c272d81bfbe964d306a1 > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 17 +++---- > .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 54 +++++++++++- > ---------- > .../amd/powerplay/hwmgr/smu7_clockpowergating.c | 9 ++-- > 3 files changed, 38 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > index 8db2655..a8c40ee 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > @@ -230,10 +230,6 @@ static int vce_v3_0_start(struct amdgpu_device > *adev) > struct amdgpu_ring *ring; > int idx, r; > > - vce_v3_0_override_vce_clock_gating(adev, true); > - if (!(adev->flags & AMD_IS_APU)) > - amdgpu_asic_set_vce_clocks(adev, 10000, 10000); > - > ring = &adev->vce.ring[0]; > WREG32(mmVCE_RB_RPTR, ring->wptr); > WREG32(mmVCE_RB_WPTR, ring->wptr); > @@ -436,9 +432,9 @@ static int vce_v3_0_hw_init(void *handle) > int r, i; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > - r = vce_v3_0_start(adev); > - if (r) > - return r; > + vce_v3_0_override_vce_clock_gating(adev, true); > + if (!(adev->flags & AMD_IS_APU)) > + amdgpu_asic_set_vce_clocks(adev, 10000, 10000); > > for (i = 0; i < adev->vce.num_rings; i++) > adev->vce.ring[i].ready = false; > @@ -766,12 +762,11 @@ static int vce_v3_0_set_powergating_state(void > *handle, > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > int ret = 0; > > - if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE)) > - return 0; > - > if (state == AMD_PG_STATE_GATE) { > + ret = vce_v3_0_stop(adev); > + if (ret) > + goto out; > adev->vce.is_powergated = true; > - /* XXX do we need a vce_v3_0_stop()? */ > } else { > ret = vce_v3_0_start(adev); > if (ret) > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > index e605cad..132bde8 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > @@ -192,34 +192,32 @@ int cz_dpm_powergate_vce(struct pp_hwmgr > *hwmgr, bool bgate) > > if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > > PHM_PlatformCaps_VCEPowerGating)) { > - if (cz_hwmgr->vce_power_gated != bgate) { > - if (bgate) { > - cgs_set_clockgating_state( > - hwmgr->device, > - > AMD_IP_BLOCK_TYPE_VCE, > - > AMD_CG_STATE_GATE); > - cgs_set_powergating_state( > - hwmgr->device, > - > AMD_IP_BLOCK_TYPE_VCE, > - > AMD_PG_STATE_GATE); > - cz_enable_disable_vce_dpm(hwmgr, false); > - cz_dpm_powerdown_vce(hwmgr); > - cz_hwmgr->vce_power_gated = true; > - } else { > - cz_dpm_powerup_vce(hwmgr); > - cz_hwmgr->vce_power_gated = false; > - cgs_set_powergating_state( > - hwmgr->device, > - > AMD_IP_BLOCK_TYPE_VCE, > - > AMD_CG_STATE_UNGATE); > - cgs_set_clockgating_state( > - hwmgr->device, > - > AMD_IP_BLOCK_TYPE_VCE, > - > AMD_PG_STATE_UNGATE); > - cz_dpm_update_vce_dpm(hwmgr); > - cz_enable_disable_vce_dpm(hwmgr, true); > - return 0; > - } > + if (bgate) { > + cgs_set_powergating_state( > + hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_PG_STATE_GATE); > + cgs_set_clockgating_state( > + hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_CG_STATE_GATE); > + cz_enable_disable_vce_dpm(hwmgr, false); > + cz_dpm_powerdown_vce(hwmgr); > + cz_hwmgr->vce_power_gated = true; > + } else { > + cz_dpm_powerup_vce(hwmgr); > + cz_hwmgr->vce_power_gated = false; > + cgs_set_clockgating_state( > + hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_PG_STATE_UNGATE); > + cgs_set_powergating_state( > + hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_CG_STATE_UNGATE); > + cz_dpm_update_vce_dpm(hwmgr); > + cz_enable_disable_vce_dpm(hwmgr, true); > + return 0; > } > } else { > cz_hwmgr->vce_power_gated = bgate; > diff --git > a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > index 0e8800f..5418f1a 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c > @@ -173,12 +173,12 @@ int smu7_powergate_vce(struct pp_hwmgr > *hwmgr, bool bgate) > { > struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr- > >backend); > > - if (data->vce_power_gated == bgate) > - return 0; > - > data->vce_power_gated = bgate; > > if (bgate) { > + cgs_set_powergating_state(hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_PG_STATE_UNGATE); > cgs_set_clockgating_state(hwmgr->device, > AMD_IP_BLOCK_TYPE_VCE, > AMD_CG_STATE_GATE); > @@ -190,6 +190,9 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, > bool bgate) > cgs_set_clockgating_state(hwmgr->device, > AMD_IP_BLOCK_TYPE_VCE, > AMD_CG_STATE_UNGATE); > + cgs_set_powergating_state(hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_PG_STATE_UNGATE); > } > return 0; > } > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
