On Mon, Jan 23, 2017 at 9:36 AM, Harry Wentland <harry.wentland at amd.com> wrote:
> From: Andrey Grodzovsky <Andrey.Grodzovsky at amd.com>
>
> Change-Id: Ia59c22ea5a78d5eecca6c62c7f50e651f29ef5f7
> Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky at amd.com>
> Acked-by: Harry Wentland <Harry.Wentland at amd.com>
> Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
> ---
> .../amd/display/dc/irq/dce110/irq_service_dce110.c | 42 ++++++++++++++++++++++
> .../amd/display/dc/irq/dce80/irq_service_dce80.c | 22 ++++++++++++
> drivers/gpu/drm/amd/display/dc/irq_types.h | 8 +++++
> 3 files changed, 72 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> index f3eda1b4eebf..4c7c85d45518 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> @@ -33,6 +33,13 @@
> #include "dce/dce_11_0_sh_mask.h"
> #include "ivsrcid/ivsrcid_vislands30.h"
>
> +#define VISLANDS30_IV_SRCID_D1_VBLANK 1
> +#define VISLANDS30_IV_SRCID_D2_VBLANK 2
> +#define VISLANDS30_IV_SRCID_D3_VBLANK 3
> +#define VISLANDS30_IV_SRCID_D4_VBLANK 4
> +#define VISLANDS30_IV_SRCID_D5_VBLANK 5
> +#define VISLANDS30_IV_SRCID_D6_VBLANK 6
> +
Add these to ivsrcid/ivsrcid_vislands30.h instead of this file? or
maybe drop ivsrcid/ivsrcid_vislands30.h if we don't need it?
Alex
> static bool hpd_ack(
> struct irq_service *irq_service,
> const struct irq_source_info *info)
> @@ -139,6 +146,22 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> .funcs = &vblank_irq_info_funcs\
> }
>
> +#define vblank_int_entry(reg_num)\
> + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> + .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\
> + .enable_mask =\
> + LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
> + .enable_value = {\
> + LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
> + ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\
> + .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\
> + .ack_mask =\
> + LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
> + .ack_value =\
> + LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
> + .funcs = &vblank_irq_info_funcs\
> + }
> +
> #define dummy_irq_entry() \
> {\
> .funcs = &dummy_irq_info_funcs\
> @@ -264,6 +287,13 @@ irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
> vupdate_int_entry(3),
> vupdate_int_entry(4),
> vupdate_int_entry(5),
> + vblank_int_entry(0),
> + vblank_int_entry(1),
> + vblank_int_entry(2),
> + vblank_int_entry(3),
> + vblank_int_entry(4),
> + vblank_int_entry(5),
> +
> };
>
> enum dc_irq_source to_dal_irq_source_dce110(
> @@ -272,6 +302,18 @@ enum dc_irq_source to_dal_irq_source_dce110(
> uint32_t ext_id)
> {
> switch (src_id) {
> + case VISLANDS30_IV_SRCID_D1_VBLANK:
> + return DC_IRQ_SOURCE_VBLANK1;
> + case VISLANDS30_IV_SRCID_D2_VBLANK:
> + return DC_IRQ_SOURCE_VBLANK2;
> + case VISLANDS30_IV_SRCID_D3_VBLANK:
> + return DC_IRQ_SOURCE_VBLANK3;
> + case VISLANDS30_IV_SRCID_D4_VBLANK:
> + return DC_IRQ_SOURCE_VBLANK4;
> + case VISLANDS30_IV_SRCID_D5_VBLANK:
> + return DC_IRQ_SOURCE_VBLANK5;
> + case VISLANDS30_IV_SRCID_D6_VBLANK:
> + return DC_IRQ_SOURCE_VBLANK6;
> case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
> return DC_IRQ_SOURCE_VUPDATE1;
> case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
> index 8b4f45389783..dd09d2b6d4a7 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
> @@ -143,6 +143,22 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> .funcs = &vblank_irq_info_funcs\
> }
>
> +#define vblank_int_entry(reg_num)\
> + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> + .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\
> + .enable_mask =\
> + LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
> + .enable_value = {\
> + LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
> + ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\
> + .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\
> + .ack_mask =\
> + LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
> + .ack_value =\
> + LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
> + .funcs = &vblank_irq_info_funcs\
> + }
> +
> #define dummy_irq_entry() \
> {\
> .funcs = &dummy_irq_info_funcs\
> @@ -246,6 +262,12 @@ irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
> vupdate_int_entry(3),
> vupdate_int_entry(4),
> vupdate_int_entry(5),
> + vblank_int_entry(0),
> + vblank_int_entry(1),
> + vblank_int_entry(2),
> + vblank_int_entry(3),
> + vblank_int_entry(4),
> + vblank_int_entry(5),
> };
>
> static const struct irq_service_funcs irq_service_funcs_dce80 = {
> diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h
> index e4b4b99a86fc..a506c2e939f5 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
> @@ -128,6 +128,13 @@ enum dc_irq_source {
> DC_IRQ_SOURCE_VUPDATE5,
> DC_IRQ_SOURCE_VUPDATE6,
>
> + DC_IRQ_SOURCE_VBLANK1,
> + DC_IRQ_SOURCE_VBLANK2,
> + DC_IRQ_SOURCE_VBLANK3,
> + DC_IRQ_SOURCE_VBLANK4,
> + DC_IRQ_SOURCE_VBLANK5,
> + DC_IRQ_SOURCE_VBLANK6,
> +
> DAL_IRQ_SOURCES_NUMBER
> };
>
> @@ -135,6 +142,7 @@ enum irq_type
> {
> IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
> IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
> + IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
> };
>
> #define DAL_VALID_IRQ_SRC_NUM(src) \
> --
> 2.9.3
>
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