> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Tuesday, January 10, 2017 6:43 AM > To: amd-gfx at lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH] drm/amd/powerplay: fix vce cg logic error. > > can fix Bug 191281: vce ib test failed. > > when vce idle, set vce clock gate, so the clock > in vce domain will be disabled. > when need to encode, disable vce clock gate, > enable the clocks to vce engine. > > Change-Id: Ic60eced7be0c1e09faca596d39ebdfde244657a2 > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> The logic with static clockgating is always somewhat counterintuitive (at least in my mind), but the corrected logic makes sense. Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > index 3bdce9e..3eccac7 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c > @@ -200,7 +200,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr > *hwmgr, bool bgate) > cgs_set_clockgating_state( > hwmgr->device, > > AMD_IP_BLOCK_TYPE_VCE, > - > AMD_CG_STATE_UNGATE); > + > AMD_CG_STATE_GATE); > cgs_set_powergating_state( > hwmgr->device, > > AMD_IP_BLOCK_TYPE_VCE, > @@ -218,7 +218,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr > *hwmgr, bool bgate) > cgs_set_clockgating_state( > hwmgr->device, > > AMD_IP_BLOCK_TYPE_VCE, > - > AMD_PG_STATE_GATE); > + > AMD_PG_STATE_UNGATE); > cz_dpm_update_vce_dpm(hwmgr); > cz_enable_disable_vce_dpm(hwmgr, true); > return 0; > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
