Yup it's held by both amdgpu_dpm_enable_uvd() and amdgpu_dpm_enable_vce()
Tom
________________________________
From: Koenig, Christian
Sent: Monday, January 9, 2017 05:32
To: Huang, Ray; Deucher, Alexander; amd-gfx at lists.freedesktop.org; StDenis, Tom
Cc: Zhu, Rex; Mao, David; Fu, Ping; Zhang, Hawking; Kuehling, Felix
Subject: Re: [PART1 PATCH v4 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6
Am 09.01.2017 um 04:00 schrieb Huang Rui:
> Signed-off-by: Huang Rui <ray.huang at amd.com>
> ---
>
> Changes from V3 -> V4:
> - use pm mutex to protect UVD clock gating status
>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 +++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 +++++++++++++++++++++++++++++++++--
> 3 files changed, 71 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 530549b..31054c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1183,6 +1183,7 @@ struct amdgpu_uvd {
> bool use_ctx_buf;
> struct amd_sched_entity entity;
> uint32_t srbm_soft_reset;
> + bool is_powergated;
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 03a35d9..e647d3e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void *handle,
> * the smc and the hw blocks
> */
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + int ret = 0;
>
> if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
> return 0;
>
> + mutex_lock(&adev->pm.mutex);
Might be that I'm wrong, but didn't Tom said the mutex is taken anyway
when this function is called?
If that's true we would certainly run into problem when we try to
acquire it again.
Christian.
> +
> if (state == AMD_PG_STATE_GATE) {
> + adev->uvd.is_powergated = true;
> uvd_v5_0_stop(adev);
> - return 0;
> } else {
> - return uvd_v5_0_start(adev);
> + ret = uvd_v5_0_start(adev);
> + if (ret)
> + goto out;
> + adev->uvd.is_powergated = false;
> + }
> +
> +out:
> + mutex_unlock(&adev->pm.mutex);
> +
> + return ret;
> +}
> +
> +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + int data;
> +
> + mutex_lock(&adev->pm.mutex);
> +
> + if (adev->uvd.is_powergated) {
> + DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> + goto out;
> }
> +
> + /* AMD_CG_SUPPORT_UVD_MGCG */
> + data = RREG32(mmUVD_CGC_CTRL);
> + if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> + *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> + mutex_unlock(&adev->pm.mutex);
> }
>
> static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> @@ -808,6 +840,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> .soft_reset = uvd_v5_0_soft_reset,
> .set_clockgating_state = uvd_v5_0_set_clockgating_state,
> .set_powergating_state = uvd_v5_0_set_powergating_state,
> + .get_clockgating_state = uvd_v5_0_get_clockgating_state,
> };
>
> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 8779d4b..2585ae9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void *handle,
> * the smc and the hw blocks
> */
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + int ret = 0;
>
> if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
> return 0;
>
> WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
>
> + mutex_lock(&adev->pm.mutex);
> +
> if (state == AMD_PG_STATE_GATE) {
> + adev->uvd.is_powergated = true;
> uvd_v6_0_stop(adev);
> - return 0;
> } else {
> - return uvd_v6_0_start(adev);
> + ret = uvd_v6_0_start(adev);
> + if (ret)
> + goto out;
> + adev->uvd.is_powergated = false;
> + }
> +
> +out:
> + mutex_unlock(&adev->pm.mutex);
> +
> + return ret;
> +}
> +
> +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + int data;
> +
> + mutex_lock(&adev->pm.mutex);
> +
> + if (adev->uvd.is_powergated) {
> + DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> + goto out;
> }
> +
> + /* AMD_CG_SUPPORT_UVD_MGCG */
> + data = RREG32(mmUVD_CGC_CTRL);
> + if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> + *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> + mutex_unlock(&adev->pm.mutex);
> }
>
> static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> @@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> .post_soft_reset = uvd_v6_0_post_soft_reset,
> .set_clockgating_state = uvd_v6_0_set_clockgating_state,
> .set_powergating_state = uvd_v6_0_set_powergating_state,
> + .get_clockgating_state = uvd_v6_0_get_clockgating_state,
> };
>
> static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20170109/0102bd56/attachment.html>
