On Fri, Jan 06, 2017 at 10:52:25AM +0100, Christian König wrote:
> Am 06.01.2017 um 08:45 schrieb Huang Rui:
> >+static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
> >+{
> >+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >+ int data;
> >+
> >+ if (adev->uvd.is_powergated) {
> >+ DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> >+ return;
> > }
>
> This is not really save. The power can be gated just in the moment
> you check the variable.
>
> Adding a spinlock or mutex to protect the variable should be sufficient.
>
Yes, a lock should be added. How about below changes:
---
>From 2d4f0232bda6bffd175ce5d10803454c3ce7dd87 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@xxxxxxx>
Date: Thu, 5 Jan 2017 21:07:02 +0800
Subject: [PATCH] drm/amdgpu: add get clockgating_state method for uvd v5&v6
Signed-off-by: Huang Rui <ray.huang at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 36 +++++++++++++++++++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 26 +++++++++++++++++++++++--
3 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 001499b..5d31e4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1183,6 +1183,8 @@ struct amdgpu_uvd {
bool use_ctx_buf;
struct amd_sched_entity entity;
uint32_t srbm_soft_reset;
+ bool is_powergated;
+ struct mutex pg_mutex;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 03a35d9..bfd94de 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -781,16 +781,47 @@ static int uvd_v5_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret;
if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
return 0;
+ mutex_lock(&adev->uvd.pg_mutex);
+
if (state == AMD_PG_STATE_GATE) {
+ adev->uvd.is_powergated = true;
uvd_v5_0_stop(adev);
- return 0;
} else {
- return uvd_v5_0_start(adev);
+ ret = uvd_v5_0_start(adev);
+ if (ret)
+ goto out;
+ adev->uvd.is_powergated = false;
+ }
+
+out:
+ mutex_unlock(&adev->uvd.pg_mutex);
+
+ return ret;
+}
+
+static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ mutex_lock(&adev->uvd.pg_mutex);
+
+ if (adev->uvd.is_powergated) {
+ DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
+ return;
}
+
+ /* AMD_CG_SUPPORT_UVD_MGCG */
+ data = RREG32(mmUVD_CGC_CTRL);
+ if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+ *flags |= AMD_CG_SUPPORT_UVD_MGCG;
+
+ mutex_unlock(&adev->uvd.pg_mutex);
}
static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
@@ -808,6 +839,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.soft_reset = uvd_v5_0_soft_reset,
.set_clockgating_state = uvd_v5_0_set_clockgating_state,
.set_powergating_state = uvd_v5_0_set_powergating_state,
+ .get_clockgating_state = uvd_v5_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8779d4b..0ce6a11 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -987,6 +987,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret;
if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
return 0;
@@ -994,11 +995,31 @@ static int uvd_v6_0_set_powergating_state(void *handle,
WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
if (state == AMD_PG_STATE_GATE) {
+ adev->uvd.is_powergated = true;
uvd_v6_0_stop(adev);
- return 0;
} else {
- return uvd_v6_0_start(adev);
+ ret = uvd_v6_0_start(adev);
+ if (ret)
+ return ret;
+ adev->uvd.is_powergated = false;
+ }
+ return 0;
+}
+
+static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ if (adev->uvd.is_powergated) {
+ DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
+ return;
}
+
+ /* AMD_CG_SUPPORT_UVD_MGCG */
+ data = RREG32(mmUVD_CGC_CTRL);
+ if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+ *flags |= AMD_CG_SUPPORT_UVD_MGCG;
}
static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
@@ -1019,6 +1040,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
.post_soft_reset = uvd_v6_0_post_soft_reset,
.set_clockgating_state = uvd_v6_0_set_clockgating_state,
.set_powergating_state = uvd_v6_0_set_powergating_state,
+ .get_clockgating_state = uvd_v6_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
--
2.7.4
