> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Marek Olšák > Sent: Monday, February 13, 2017 11:58 AM > To: amd-gfx at lists.freedesktop.org > Subject: [PATCH] drm/radeon: allow unaligned shader loads on CIK > > From: Marek Olšák <marek.olsak at amd.com> > > Signed-off-by: Marek Olšák <marek.olsak at amd.com> Add a better patch description. With that fixed: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/radeon/cik.c | 7 +++++-- > drivers/gpu/drm/radeon/radeon_drv.c | 3 ++- > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index f6ff41a..ac0d939 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -28,20 +28,23 @@ > #include "radeon.h" > #include "radeon_asic.h" > #include "radeon_audio.h" > #include "cikd.h" > #include "atom.h" > #include "cik_blit_shaders.h" > #include "radeon_ucode.h" > #include "clearstate_ci.h" > #include "radeon_kfd.h" > > +#define SH_MEM_CONFIG_GFX_DEFAULT \ > + ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) > + > MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_me.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_ce.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_mec.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_mc.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin"); > MODULE_FIRMWARE("radeon/BONAIRE_smc.bin"); > > @@ -5580,21 +5583,21 @@ static int cik_pcie_gart_enable(struct > radeon_device *rdev) > tmp &= ~BYPASS_VM; > WREG32(CHUB_CONTROL, tmp); > } > > /* XXX SH_MEM regs */ > /* where to put LDS, scratch, GPUVM in FSA64 space */ > mutex_lock(&rdev->srbm_mutex); > for (i = 0; i < 16; i++) { > cik_srbm_select(rdev, 0, 0, 0, i); > /* CP and shaders */ > - WREG32(SH_MEM_CONFIG, 0); > + WREG32(SH_MEM_CONFIG, > SH_MEM_CONFIG_GFX_DEFAULT); > WREG32(SH_MEM_APE1_BASE, 1); > WREG32(SH_MEM_APE1_LIMIT, 0); > WREG32(SH_MEM_BASES, 0); > /* SDMA GFX */ > WREG32(SDMA0_GFX_VIRTUAL_ADDR + > SDMA0_REGISTER_OFFSET, 0); > WREG32(SDMA0_GFX_APE1_CNTL + > SDMA0_REGISTER_OFFSET, 0); > WREG32(SDMA0_GFX_VIRTUAL_ADDR + > SDMA1_REGISTER_OFFSET, 0); > WREG32(SDMA0_GFX_APE1_CNTL + > SDMA1_REGISTER_OFFSET, 0); > /* XXX SDMA RLC - todo */ > } > @@ -5787,21 +5790,21 @@ void cik_vm_flush(struct radeon_device *rdev, > struct radeon_ring *ring, > radeon_ring_write(ring, 0); > radeon_ring_write(ring, VMID(vm_id)); > > radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); > radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | > WRITE_DATA_DST_SEL(0))); > radeon_ring_write(ring, SH_MEM_BASES >> 2); > radeon_ring_write(ring, 0); > > radeon_ring_write(ring, 0); /* SH_MEM_BASES */ > - radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */ > + radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* > SH_MEM_CONFIG */ > radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ > radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ > > radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); > radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | > WRITE_DATA_DST_SEL(0))); > radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); > radeon_ring_write(ring, 0); > radeon_ring_write(ring, VMID(0)); > > diff --git a/drivers/gpu/drm/radeon/radeon_drv.c > b/drivers/gpu/drm/radeon/radeon_drv.c > index 30bd4a6..2e5d680 100644 > --- a/drivers/gpu/drm/radeon/radeon_drv.c > +++ b/drivers/gpu/drm/radeon/radeon_drv.c > @@ -91,23 +91,24 @@ > * CS to GPU on >= r600 > * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command > parsing support > * 2.42.0 - Add VCE/VUI (Video Usability Information) support > * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER > * 2.44.0 - SET_APPEND_CNT packet3 support > * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI > * 2.46.0 - Add PFP_SYNC_ME support on evergreen > * 2.47.0 - Add UVD_NO_OP register support > * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI > * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible > values > + * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) > */ > #define KMS_DRIVER_MAJOR 2 > -#define KMS_DRIVER_MINOR 49 > +#define KMS_DRIVER_MINOR 50 > #define KMS_DRIVER_PATCHLEVEL 0 > int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); > int radeon_driver_unload_kms(struct drm_device *dev); > void radeon_driver_lastclose_kms(struct drm_device *dev); > int radeon_driver_open_kms(struct drm_device *dev, struct drm_file > *file_priv); > void radeon_driver_postclose_kms(struct drm_device *dev, > struct drm_file *file_priv); > void radeon_driver_preclose_kms(struct drm_device *dev, > struct drm_file *file_priv); > int radeon_suspend_kms(struct drm_device *dev, bool suspend, > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
