> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Monday, February 13, 2017 10:28 AM > To: amd-gfx at lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH] Add new gmc/smu registers > > Signed-off-by: Tom St Denis <tom.stdenis at amd.com> Acked-by: Alex Deucher <alexander.deucher at amd.com> > --- > src/lib/ip/gmc60_bits.i | 2 ++ > src/lib/ip/smu701_bits.i | 4 ++++ > src/lib/ip/smu701_regs.i | 1 + > src/lib/ip/smu711_bits.i | 4 ++++ > src/lib/ip/smu711_regs.i | 1 + > src/lib/ip/smu712_bits.i | 4 ++++ > src/lib/ip/smu712_regs.i | 1 + > src/lib/ip/smu713_bits.i | 4 ++++ > src/lib/ip/smu713_regs.i | 1 + > 9 files changed, 22 insertions(+) > > diff --git a/src/lib/ip/gmc60_bits.i b/src/lib/ip/gmc60_bits.i > index 746dd64fb392..4e4c052f6e79 100644 > --- a/src/lib/ip/gmc60_bits.i > +++ b/src/lib/ip/gmc60_bits.i > @@ -3230,6 +3230,8 @@ static struct umr_bitfield > mmVM_PRT_APERTURE3_HIGH_ADDR[] = { > static struct umr_bitfield mmVM_PRT_CNTL[] = { > { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default }, > { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default > }, > + { "CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS", 0, 0, > &umr_bitfield_default }, > + { "TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS", 1, 1, > &umr_bitfield_default }, > }; > static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = { > { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default }, > diff --git a/src/lib/ip/smu701_bits.i b/src/lib/ip/smu701_bits.i > index 972d8b74b5db..2f50eb9f0b67 100644 > --- a/src/lib/ip/smu701_bits.i > +++ b/src/lib/ip/smu701_bits.i > @@ -4391,6 +4391,10 @@ static struct umr_bitfield > ixCG_FREQ_TRAN_VOTING_7[] = { > static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = { > { "VBI_PREDICTION", 0, 31, &umr_bitfield_default }, > }; > +static struct umr_bitfield ixCURRENT_PG_STATUS[] = { > + { "VCE_PG_STATUS", 1, 1, &umr_bitfield_default }, > + { "UVD_PG_STATUS", 2, 2, &umr_bitfield_default }, > +}; > static struct umr_bitfield ixSCLK_MIN_DIV[] = { > { "FRACV", 0, 11, &umr_bitfield_default }, > { "INTV", 12, 18, &umr_bitfield_default }, > diff --git a/src/lib/ip/smu701_regs.i b/src/lib/ip/smu701_regs.i > index 63f85e1173cc..3ff965359c89 100644 > --- a/src/lib/ip/smu701_regs.i > +++ b/src/lib/ip/smu701_regs.i > @@ -1091,6 +1091,7 @@ > { "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, > &ixCG_FREQ_TRAN_VOTING_6[0], > sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[ > 0]), 0, 0 }, > { "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, > &ixCG_FREQ_TRAN_VOTING_7[0], > sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[ > 0]), 0, 0 }, > { "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, > &ixCG_DISPLAY_GAP_CNTL2[0], > sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, > 0 }, > + { "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, > &ixCURRENT_PG_STATUS[0], > sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 }, > { "ixSCLK_MIN_DIV", REG_SMC, 0xc0200308, &ixSCLK_MIN_DIV[0], > sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 }, > { "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, > &ixLCLK_DEEP_SLEEP_CNTL2[0], > sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, > 0 }, > { "ixCG_THERMAL_CTRL", REG_SMC, 0xc0300004, > &ixCG_THERMAL_CTRL[0], > sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 }, > diff --git a/src/lib/ip/smu711_bits.i b/src/lib/ip/smu711_bits.i > index 6d803259e970..afd90220d5d5 100644 > --- a/src/lib/ip/smu711_bits.i > +++ b/src/lib/ip/smu711_bits.i > @@ -3577,6 +3577,10 @@ static struct umr_bitfield > ixCG_FREQ_TRAN_VOTING_7[] = { > static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = { > { "VBI_PREDICTION", 0, 31, &umr_bitfield_default }, > }; > +static struct umr_bitfield ixCURRENT_PG_STATUS[] = { > + { "VCE_PG_STATUS", 1, 1, &umr_bitfield_default }, > + { "UVD_PG_STATUS", 2, 2, &umr_bitfield_default }, > +}; > static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = { > { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default }, > { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default }, > diff --git a/src/lib/ip/smu711_regs.i b/src/lib/ip/smu711_regs.i > index 6e66ecd4ac09..efeac147288e 100644 > --- a/src/lib/ip/smu711_regs.i > +++ b/src/lib/ip/smu711_regs.i > @@ -886,6 +886,7 @@ > { "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, > &ixCG_FREQ_TRAN_VOTING_6[0], > sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[ > 0]), 0, 0 }, > { "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, > &ixCG_FREQ_TRAN_VOTING_7[0], > sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[ > 0]), 0, 0 }, > { "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, > &ixCG_DISPLAY_GAP_CNTL2[0], > sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, > 0 }, > + { "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, > &ixCURRENT_PG_STATUS[0], > sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 }, > { "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, > &ixLCLK_DEEP_SLEEP_CNTL2[0], > sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, > 0 }, > { "ixVDDGFX_IDLE_PARAMETER", REG_SMC, 0xc020036c, > &ixVDDGFX_IDLE_PARAMETER[0], > sizeof(ixVDDGFX_IDLE_PARAMETER)/sizeof(ixVDDGFX_IDLE_PARAMETER[0] > ), 0, 0 }, > { "ixVDDGFX_IDLE_CONTROL", REG_SMC, 0xc0200370, > &ixVDDGFX_IDLE_CONTROL[0], > sizeof(ixVDDGFX_IDLE_CONTROL)/sizeof(ixVDDGFX_IDLE_CONTROL[0]), 0, 0 > }, > diff --git a/src/lib/ip/smu712_bits.i b/src/lib/ip/smu712_bits.i > index 2c5af08f710c..45776abe55da 100644 > --- a/src/lib/ip/smu712_bits.i > +++ b/src/lib/ip/smu712_bits.i > @@ -4269,6 +4269,10 @@ static struct umr_bitfield > ixCG_FREQ_TRAN_VOTING_7[] = { > static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = { > { "VBI_PREDICTION", 0, 31, &umr_bitfield_default }, > }; > +static struct umr_bitfield ixCURRENT_PG_STATUS[] = { > + { "VCE_PG_STATUS", 1, 1, &umr_bitfield_default }, > + { "UVD_PG_STATUS", 2, 2, &umr_bitfield_default }, > +}; > static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = { > { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default }, > { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default }, > diff --git a/src/lib/ip/smu712_regs.i b/src/lib/ip/smu712_regs.i > index 1b858325b6e2..eb030979eaec 100644 > --- a/src/lib/ip/smu712_regs.i > +++ b/src/lib/ip/smu712_regs.i > @@ -1009,6 +1009,7 @@ > { "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, > &ixCG_FREQ_TRAN_VOTING_6[0], > sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[ > 0]), 0, 0 }, > { "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, > &ixCG_FREQ_TRAN_VOTING_7[0], > sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[ > 0]), 0, 0 }, > { "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, > &ixCG_DISPLAY_GAP_CNTL2[0], > sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, > 0 }, > + { "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, > &ixCURRENT_PG_STATUS[0], > sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 }, > { "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, > &ixLCLK_DEEP_SLEEP_CNTL2[0], > sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, > 0 }, > { "ixPWR_CKS_ENABLE", REG_SMC, 0xc020034c, > &ixPWR_CKS_ENABLE[0], > sizeof(ixPWR_CKS_ENABLE)/sizeof(ixPWR_CKS_ENABLE[0]), 0, 0 }, > { "ixPWR_CKS_CNTL", REG_SMC, 0xc0200350, &ixPWR_CKS_CNTL[0], > sizeof(ixPWR_CKS_CNTL)/sizeof(ixPWR_CKS_CNTL[0]), 0, 0 }, > diff --git a/src/lib/ip/smu713_bits.i b/src/lib/ip/smu713_bits.i > index b166f936d7e6..36e01e79a35c 100644 > --- a/src/lib/ip/smu713_bits.i > +++ b/src/lib/ip/smu713_bits.i > @@ -3874,6 +3874,10 @@ static struct umr_bitfield > ixCG_FREQ_TRAN_VOTING_7[] = { > static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = { > { "VBI_PREDICTION", 0, 31, &umr_bitfield_default }, > }; > +static struct umr_bitfield ixCURRENT_PG_STATUS[] = { > + { "VCE_PG_STATUS", 1, 1, &umr_bitfield_default }, > + { "UVD_PG_STATUS", 2, 2, &umr_bitfield_default }, > +}; > static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = { > { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default }, > { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default }, > diff --git a/src/lib/ip/smu713_regs.i b/src/lib/ip/smu713_regs.i > index 61a8af01c246..0f1d79aa2b9f 100644 > --- a/src/lib/ip/smu713_regs.i > +++ b/src/lib/ip/smu713_regs.i > @@ -886,6 +886,7 @@ > { "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, > &ixCG_FREQ_TRAN_VOTING_6[0], > sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[ > 0]), 0, 0 }, > { "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, > &ixCG_FREQ_TRAN_VOTING_7[0], > sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[ > 0]), 0, 0 }, > { "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, > &ixCG_DISPLAY_GAP_CNTL2[0], > sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, > 0 }, > + { "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, > &ixCURRENT_PG_STATUS[0], > sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 }, > { "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, > &ixLCLK_DEEP_SLEEP_CNTL2[0], > sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, > 0 }, > { "ixPWR_CKS_ENABLE", REG_SMC, 0xc020034c, > &ixPWR_CKS_ENABLE[0], > sizeof(ixPWR_CKS_ENABLE)/sizeof(ixPWR_CKS_ENABLE[0]), 0, 0 }, > { "ixPWR_CKS_CNTL", REG_SMC, 0xc0200350, &ixPWR_CKS_CNTL[0], > sizeof(ixPWR_CKS_CNTL)/sizeof(ixPWR_CKS_CNTL[0]), 0, 0 }, > -- > 2.11.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
