On 08.02.2017 16:06, Christian König wrote:
> From: Christian König <christian.koenig at amd.com>
>
> Just a simple test if PRT works or not.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Too bad we can't ask the kernel whether a VM fault happened :/
I haven't pushed my libdrm patches yet because my understanding is that
the kernel changes should come first. I saw your v3 series, I'll
probably give it a go with my Mesa changes tomorrow.
Cheers,
Nicolai
> ---
> tests/amdgpu/basic_tests.c | 66 ++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 64 insertions(+), 2 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index bfda21b..24dd605 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -48,6 +48,7 @@ static void amdgpu_command_submission_compute(void);
> static void amdgpu_command_submission_sdma(void);
> static void amdgpu_userptr_test(void);
> static void amdgpu_semaphore_test(void);
> +static void amdgpu_prt_test(void);
>
> static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
> static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
> @@ -61,6 +62,7 @@ CU_TestInfo basic_tests[] = {
> { "Command submission Test (Compute)", amdgpu_command_submission_compute },
> { "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
> { "SW semaphore Test", amdgpu_semaphore_test },
> + { "PRT Test", amdgpu_prt_test },
> CU_TEST_INFO_NULL,
> };
> #define BUFFER_SIZE (8 * 1024)
> @@ -734,7 +736,6 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
>
> /* prepare CS */
> CU_ASSERT_NOT_EQUAL(pm4_src, NULL);
> - CU_ASSERT_NOT_EQUAL(resources, NULL);
> CU_ASSERT_NOT_EQUAL(ib_info, NULL);
> CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
> CU_ASSERT_TRUE(pm4_dw <= 1024);
> @@ -759,7 +760,8 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
> ibs_request->ibs = ib_info;
> ibs_request->fence_info.handle = NULL;
>
> - memcpy(all_res, resources, sizeof(resources[0]) * res_cnt);
> + if (resources)
> + memcpy(all_res, resources, sizeof(resources[0]) * res_cnt);
> all_res[res_cnt] = ib_result_handle;
>
> r = amdgpu_bo_list_create(device_handle, res_cnt+1, all_res,
> @@ -1208,3 +1210,63 @@ static void amdgpu_userptr_test(void)
> r = amdgpu_cs_ctx_free(context_handle);
> CU_ASSERT_EQUAL(r, 0);
> }
> +
> +static void amdgpu_prt_test(void)
> +{
> + int i, r, j;
> + uint32_t *pm4 = NULL;
> + uint64_t bo_mc;
> + int pm4_dw = 256;
> + int sdma_write_length = 4;
> + amdgpu_context_handle context_handle;
> + struct amdgpu_cs_ib_info *ib_info;
> + struct amdgpu_cs_request *ibs_request;
> + amdgpu_va_handle va_handle;
> +
> + pm4 = calloc(pm4_dw, sizeof(*pm4));
> + CU_ASSERT_NOT_EQUAL(pm4, NULL);
> +
> + ib_info = calloc(1, sizeof(*ib_info));
> + CU_ASSERT_NOT_EQUAL(ib_info, NULL);
> +
> + ibs_request = calloc(1, sizeof(*ibs_request));
> + CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + r = amdgpu_va_range_alloc(device_handle,
> + amdgpu_gpu_va_range_general,
> + BUFFER_SIZE, 1, 0, &bo_mc,
> + &va_handle, 0);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + /*r = amdgpu_bo_va_op_raw(device_handle, NULL, 0, BUFFER_SIZE, bo_mc,
> + AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
> + CU_ASSERT_EQUAL(r, 0);*/
> +
> + j = i = 0;
> + pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
> + pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
> + pm4[i++] = 0xfffffffc & bo_mc;
> + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
> + while(j++ < sdma_write_length)
> + pm4[i++] = 0xdeadbeaf;
> +
> + amdgpu_test_exec_cs_helper(context_handle,
> + AMDGPU_HW_IP_GFX, 0,
> + i, pm4, 0, NULL,
> + ib_info, ibs_request);
> + free(ibs_request);
> + free(ib_info);
> + free(pm4);
> +
> + r = amdgpu_bo_va_op_raw(device_handle, NULL, 0, BUFFER_SIZE, bo_mc,
> + AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_UNMAP);
> + CU_ASSERT_EQUAL(r, 0);
> + r = amdgpu_va_range_free(va_handle);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + CU_ASSERT_EQUAL(r, 0);
> +}
>
