> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Tuesday, February 07, 2017 1:11 AM > To: amd-gfx at lists.freedesktop.org > Cc: Xue, Ken > Subject: [PATCH 13/20] Refine handshake between guest and host by > mailbox > > From: Ken Xue <Ken.Xue at amd.com> > > Change-Id: If3a7d05824847234759b86563e8052949e171972 > Signed-off-by: Ken Xue <Ken.Xue at amd.com> Not too familiar with the mailbox stuff. Acked-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 26 > +++++++++++++++++++++++++- > 1 file changed, 25 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > index d2622b6..5fe4aad 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct > amdgpu_device *adev) > static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev) > { > u32 reg; > + int timeout = VI_MAILBOX_TIMEDOUT; > + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, > RCV_MSG_VALID); > > reg = RREG32(mmMAILBOX_CONTROL); > reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1); > WREG32(mmMAILBOX_CONTROL, reg); > + > + /*Wait for RCV_MSG_VALID to be 0*/ > + reg = RREG32(mmMAILBOX_CONTROL); > + while (reg & mask) { > + if (timeout <= 0) { > + pr_err("RCV_MSG_VALID is not cleared\n"); > + break; > + } > + mdelay(1); > + timeout -=1; > + > + reg = RREG32(mmMAILBOX_CONTROL); > + } > } > > static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool > val) > @@ -339,6 +354,8 @@ static void xgpu_vi_mailbox_trans_msg(struct > amdgpu_device *adev, > { > u32 reg; > > + xgpu_vi_mailbox_send_ack(adev); > + > reg = RREG32(mmMAILBOX_MSGBUF_TRN_DW0); > reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0, > MSGBUF_DATA, event); > @@ -351,6 +368,11 @@ static int xgpu_vi_mailbox_rcv_msg(struct > amdgpu_device *adev, > enum idh_event event) > { > u32 reg; > + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, > RCV_MSG_VALID); > + > + reg = RREG32(mmMAILBOX_CONTROL); > + if (!(reg & mask)) > + return -ENOENT; > > reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0); > if (reg != event) > @@ -419,7 +441,9 @@ static int xgpu_vi_send_access_requests(struct > amdgpu_device *adev, > xgpu_vi_mailbox_set_valid(adev, false); > > /* start to check msg if request is idh_req_gpu_init_access */ > - if (request == IDH_REQ_GPU_INIT_ACCESS) { > + if (request == IDH_REQ_GPU_INIT_ACCESS || > + request == IDH_REQ_GPU_FINI_ACCESS || > + request == IDH_REQ_GPU_RESET_ACCESS) { > r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); > if (r) > return r; > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
