> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Tuesday, February 07, 2017 1:11 AM > To: amd-gfx at lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 02/20] drm/amdgpu:cg & pg are not applied on VF > > Change-Id: I93a4e97f1d24a289ab20c2a62371f3e303322587 > Signed-off-by: Monk Liu <Monk.Liu at amd.com> Please add a better patch description. Something like, CG and PG are not controlled by the PF and are not applicable to the VFs. With that, Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 9 +++++++++ > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++ > 4 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 0a75021..1e170ab 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -5833,6 +5833,9 @@ static int gfx_v8_0_set_powergating_state(void > *handle, > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > bool enable = (state == AMD_PG_STATE_GATE) ? true : false; > > + if (amdgpu_sriov_vf(adev)) > + return 0; > + > switch (adev->asic_type) { > case CHIP_CARRIZO: > case CHIP_STONEY: > @@ -5890,6 +5893,9 @@ static void gfx_v8_0_get_clockgating_state(void > *handle, u32 *flags) > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > int data; > > + if (amdgpu_sriov_vf(adev)) > + *flags = 0; > + > /* AMD_CG_SUPPORT_GFX_MGCG */ > data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); > if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK)) > @@ -6403,6 +6409,9 @@ static int gfx_v8_0_set_clockgating_state(void > *handle, > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > + if (amdgpu_sriov_vf(adev)) > + return 0; > + > switch (adev->asic_type) { > case CHIP_FIJI: > case CHIP_CARRIZO: > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index 7669b32..22c52d6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -1427,6 +1427,9 @@ static int gmc_v8_0_set_clockgating_state(void > *handle, > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > + if (amdgpu_sriov_vf(adev)) > + return 0; > + > switch (adev->asic_type) { > case CHIP_FIJI: > fiji_update_mc_medium_grain_clock_gating(adev, > @@ -1451,6 +1454,9 @@ static void gmc_v8_0_get_clockgating_state(void > *handle, u32 *flags) > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > int data; > > + if (amdgpu_sriov_vf(adev)) > + *flags = 0; > + > /* AMD_CG_SUPPORT_MC_MGCG */ > data = RREG32(mmMC_HUB_MISC_HUB_CG); > if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > index 25602c4..9394ca6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > @@ -1512,6 +1512,9 @@ static int sdma_v3_0_set_clockgating_state(void > *handle, > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > + if (amdgpu_sriov_vf(adev)) > + return 0; > + > switch (adev->asic_type) { > case CHIP_FIJI: > case CHIP_CARRIZO: > @@ -1538,6 +1541,9 @@ static void sdma_v3_0_get_clockgating_state(void > *handle, u32 *flags) > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > int data; > > + if (amdgpu_sriov_vf(adev)) > + *flags = 0; > + > /* AMD_CG_SUPPORT_SDMA_MGCG */ > data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); > if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) > diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c > b/drivers/gpu/drm/amd/amdgpu/vi.c > index 89b0dfe..aeef3c9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/vi.c > @@ -1391,6 +1391,9 @@ static int vi_common_set_clockgating_state(void > *handle, > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > + if (amdgpu_sriov_vf(adev)) > + return 0; > + > switch (adev->asic_type) { > case CHIP_FIJI: > vi_update_bif_medium_grain_light_sleep(adev, > @@ -1435,6 +1438,9 @@ static void vi_common_get_clockgating_state(void > *handle, u32 *flags) > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > int data; > > + if (amdgpu_sriov_vf(adev)) > + *flags = 0; > + > /* AMD_CG_SUPPORT_BIF_LS */ > data = RREG32_PCIE(ixPCIE_CNTL2); > if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
