On 2017å¹´12æ??14æ?¥ 02:33, Christian König wrote:
> Am 13.12.2017 um 08:19 schrieb Chunming Zhou:
>> Change-Id: Ic1f39d3bc853e9e4259d3e03a22920eda822eec5
>> Signed-off-by: Chunming Zhou <david1.zhou at amd.com>
>
> You dropped reversing the ordering and replaced that with noting the
> root level separately? Nifty idea.
Yes.
>
> Just please drop AMDGPU_VM_SUBPTB, translate further is something we
> hopefully will only use the first and last time for Raven.
dropped, please review the v2.
>
> So I would like to keep that completely transparent to the VM code and
> do the patching in the GMC specific implementation for Raven.
go ahead, you can send your 2+1 patch again based on enumerate.
Regards,
David Zhou
>
> Christian.
>
>> ---
>> Â drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 69
>> +++++++++++++++++++++++++---------
>> Â drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 14 +++++++
>> Â 2 files changed, 66 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 709587d8a77f..fc858ddf9319 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -148,12 +148,29 @@ struct amdgpu_prt_cb {
>> Â static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â unsigned level)
>> Â {
>> -Â Â Â if (level != adev->vm_manager.num_level)
>> -Â Â Â Â Â Â Â return 9 * (adev->vm_manager.num_level - level - 1) +
>> +Â Â Â unsigned shift = 0xff;
>> +
>> +Â Â Â switch (level) {
>> +Â Â Â case AMDGPU_VM_PDB2:
>> +Â Â Â case AMDGPU_VM_PDB1:
>> +Â Â Â case AMDGPU_VM_PDB0:
>> +Â Â Â Â Â Â Â shift = 9 * (adev->vm_manager.last_level - level - 1) +
>> Â Â Â Â Â Â Â Â Â Â Â Â Â adev->vm_manager.block_size;
>> -Â Â Â else
>> -Â Â Â Â Â Â Â /* For the page tables on the leaves */
>> -Â Â Â Â Â Â Â return 0;
>> +Â Â Â Â Â Â Â break;
>> +Â Â Â case AMDGPU_VM_PTB:
>> +Â Â Â Â Â Â Â if (adev->vm_manager.last_level == AMDGPU_VM_PTB)
>> +Â Â Â Â Â Â Â Â Â Â Â shift = 0;
>> +Â Â Â Â Â Â Â else
>> +Â Â Â Â Â Â Â Â Â Â Â shift = adev->vm_manager.block_size;
>> +Â Â Â Â Â Â Â break;
>> +Â Â Â case AMDGPU_VM_SUBPTB:
>> +Â Â Â Â Â Â Â shift = 0;
>> +Â Â Â Â Â Â Â break;
>> +Â Â Â default:
>> +Â Â Â Â Â Â Â dev_err(adev->dev, "the level%d isn't supported.\n", level);
>> +Â Â Â }
>> +
>> +Â Â Â return shift;
>> Â }
>> Â Â /**
>> @@ -166,12 +183,13 @@ static unsigned amdgpu_vm_level_shift(struct
>> amdgpu_device *adev,
>> Â static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â unsigned level)
>> Â {
>> -Â Â Â unsigned shift = amdgpu_vm_level_shift(adev, 0);
>> +Â Â Â unsigned shift = amdgpu_vm_level_shift(adev,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â adev->vm_manager.root_level);
>> Â -Â Â Â if (level == 0)
>> +Â Â Â if (level == adev->vm_manager.root_level)
>> Â Â Â Â Â Â Â Â Â /* For the root directory */
>> Â Â Â Â Â Â Â Â Â return round_up(adev->vm_manager.max_pfn, 1 << shift) >>
>> shift;
>> -Â Â Â else if (level != adev->vm_manager.num_level)
>> +Â Â Â else if (level != adev->vm_manager.last_level)
>> Â Â Â Â Â Â Â Â Â /* Everything in between */
>> Â Â Â Â Â Â Â Â Â return 512;
>> Â Â Â Â Â else
>> @@ -385,7 +403,7 @@ static int amdgpu_vm_alloc_levels(struct
>> amdgpu_device *adev,
>> Â Â Â Â Â Â Â Â Â Â Â Â Â spin_unlock(&vm->status_lock);
>> Â Â Â Â Â Â Â Â Â }
>> Â -Â Â Â Â Â Â Â if (level < adev->vm_manager.num_level) {
>> +Â Â Â Â Â Â Â if (level < adev->vm_manager.last_level) {
>> Â Â Â Â Â Â Â Â Â Â Â Â Â uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
>> Â Â Â Â Â Â Â Â Â Â Â Â Â uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ((1 << shift) - 1);
>> @@ -431,7 +449,8 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
>> Â Â Â Â Â saddr /= AMDGPU_GPU_PAGE_SIZE;
>> Â Â Â Â Â eaddr /= AMDGPU_GPU_PAGE_SIZE;
>> Â -Â Â Â return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr,
>> eaddr, 0);
>> +Â Â Â return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â adev->vm_manager.root_level);
>> Â }
>> Â Â /**
>> @@ -1247,7 +1266,8 @@ int amdgpu_vm_update_directories(struct
>> amdgpu_device *adev,
>> Â Â Â Â Â return 0;
>> Â Â error:
>> -Â Â Â amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0);
>> +Â Â Â amdgpu_vm_invalidate_level(adev, vm, &vm->root,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â adev->vm_manager.root_level);
>> Â Â Â Â Â amdgpu_job_free(job);
>> Â Â Â Â Â return r;
>> Â }
>> @@ -1266,7 +1286,7 @@ void amdgpu_vm_get_entry(struct
>> amdgpu_pte_update_params *p, uint64_t addr,
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct amdgpu_vm_pt **entry,
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct amdgpu_vm_pt **parent)
>> Â {
>> -Â Â Â unsigned level = 0;
>> +Â Â Â unsigned level = p->adev->vm_manager.root_level;
>> Â Â Â Â Â Â *parent = NULL;
>> Â Â Â Â Â *entry = &p->vm->root;
>> @@ -1278,7 +1298,7 @@ void amdgpu_vm_get_entry(struct
>> amdgpu_pte_update_params *p, uint64_t addr,
>> Â Â Â Â Â Â Â Â Â addr &= (1ULL << shift) - 1;
>> Â Â Â Â Â }
>> Â -Â Â Â if (level != p->adev->vm_manager.num_level)
>> +Â Â Â if (level != p->adev->vm_manager.last_level)
>> Â Â Â Â Â Â Â Â Â *entry = NULL;
>> Â }
>> Â @@ -1320,7 +1340,7 @@ static void
>> amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
>> Â Â Â Â Â Â Â Â Â return;
>> Â Â Â Â Â entry->huge = !!(flags & AMDGPU_PDE_PTE);
>> Â -Â Â Â amdgpu_gart_get_vm_pde(p->adev, p->adev->vm_manager.num_level
>> - 1,
>> +Â Â Â amdgpu_gart_get_vm_pde(p->adev, p->adev->vm_manager.last_level - 1,
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &dst, &flags);
>> Â Â Â Â Â Â if (use_cpu_update) {
>> @@ -1636,7 +1656,8 @@ static int amdgpu_vm_bo_update_mapping(struct
>> amdgpu_device *adev,
>> Â Â error_free:
>> Â Â Â Â Â amdgpu_job_free(job);
>> -Â Â Â amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0);
>> +Â Â Â amdgpu_vm_invalidate_level(adev, vm, &vm->root,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â adev->vm_manager.root_level);
>> Â Â Â Â Â return r;
>> Â }
>> Â @@ -2552,7 +2573,20 @@ void amdgpu_vm_adjust_size(struct
>> amdgpu_device *adev, uint32_t vm_size,
>> Â Â Â Â Â Â Â Â Â tmp >>= amdgpu_vm_block_size - 9;
>> Â Â Â Â Â tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
>> Â Â Â Â Â adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
>> -
>> +Â Â Â switch (adev->vm_manager.num_level) {
>> +Â Â Â case 3:
>> +Â Â Â Â Â Â Â adev->vm_manager.root_level = AMDGPU_VM_PDB2;
>> +Â Â Â Â Â Â Â break;
>> +Â Â Â case 2:
>> +Â Â Â Â Â Â Â adev->vm_manager.root_level = AMDGPU_VM_PDB1;
>> +Â Â Â Â Â Â Â break;
>> +Â Â Â case 1:
>> +Â Â Â Â Â Â Â adev->vm_manager.root_level = AMDGPU_VM_PDB0;
>> +Â Â Â Â Â Â Â break;
>> +Â Â Â default:
>> +Â Â Â Â Â Â Â dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
>> +Â Â Â }
>> +Â Â Â adev->vm_manager.last_level = AMDGPU_VM_PTB;
>> Â Â Â Â Â /* block size depends on vm size and hw setup*/
>> Â Â Â Â Â if (amdgpu_vm_block_size != -1)
>> Â Â Â Â Â Â Â Â Â adev->vm_manager.block_size =
>> @@ -2782,7 +2816,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev,
>> struct amdgpu_vm *vm)
>> Â Â Â Â Â if (r) {
>> Â Â Â Â Â Â Â Â Â dev_err(adev->dev, "Leaking page tables because BO
>> reservation failed\n");
>> Â Â Â Â Â } else {
>> -Â Â Â Â Â Â Â amdgpu_vm_free_levels(adev, &vm->root, 0);
>> +Â Â Â Â Â Â Â amdgpu_vm_free_levels(adev, &vm->root,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â adev->vm_manager.root_level);
>> Â Â Â Â Â Â Â Â Â amdgpu_bo_unreserve(root);
>> Â Â Â Â Â }
>> Â Â Â Â Â amdgpu_bo_unref(&root);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index e52bf980669f..9d5b2ce5e527 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -120,6 +120,18 @@ struct amdgpu_bo_list_entry;
>> Â #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
>> Â #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
>> Â +/* VMPT level enumerate, and the hiberachy is:
>> + * PDB2->PDB1->PDB0->PTB->SUBPTB
>> + */
>> +enum amdgpu_vm_level {
>> +Â Â Â AMDGPU_VM_PDB2,
>> +Â Â Â AMDGPU_VM_PDB1,
>> +Â Â Â AMDGPU_VM_PDB0,
>> +Â Â Â AMDGPU_VM_PTB,
>> +Â Â Â AMDGPU_VM_SUBPTB,
>> +Â Â Â AMDGPU_VM_LEVELS
>> +};
>> +
>> Â /* base structure for tracking BO usage in a VM */
>> Â struct amdgpu_vm_bo_base {
>> Â Â Â Â Â /* constant after initialization */
>> @@ -236,6 +248,8 @@ struct amdgpu_vm_manager {
>>      uint32_t               num_level;
>>      uint32_t               block_size;
>>      uint32_t               fragment_size;
>> +   uint32_t               root_level;
>> +   uint32_t               last_level;
>>      /* vram base address for page table entry */
>> Â Â Â Â Â u64Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â vram_base_offset;
>> Â Â Â Â Â /* vm pte handling */
>
