Yeah, I realized this later last night. I'm going to do some more debugging to track down the real problem today.
For now, this seems to have moved around IB allocations enough to hide the problem so our merge today seems to have passed PSDB. But like I said, at best I've hidden the problem, not fixed it.
Regards,
Felix
________________________________________
From: Christian König <deathsimple@xxxxxxxxxxx>
Sent: Thursday, August 31, 2017 3:06:37 AM
To: Kuehling, Felix; amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Fix IB allocation sizes for page table updates
Am 30.08.2017 um 23:08 schrieb Felix Kuehling:
> set_pte_pde commands need 10 dwords.
But is only used when we write more than 3 consecutive entries, before
that we use write_pte which uses only 6 dw.
See amdgpu_vm_do_set_ptes() in amdgpu_vm.c
Regards,
Christian.
>
> Signed-off-by: Felix Kuehling <Felix.Kuehling at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 4cdfb70..587a166 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -1037,7 +1037,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
> ndw = 64;
>
> /* assume the worst case */
> - ndw += parent->last_entry_used * 6;
> + ndw += parent->last_entry_used * 10;
>
> pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
>
> @@ -1545,7 +1545,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
> ndw = 64;
>
> /* one PDE write for each huge page */
> - ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
> + ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 10;
>
> if (src) {
> /* only copy commands needed */
