> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Tuesday, August 29, 2017 5:14 AM > To: amd-gfx at lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay. > > This feature is for UMD to run benchmark in a > power state that is as steady as possible. kmd > need to fix the power state as stable as possible. > now, kmd support four level: > profile_standard,peak,min_sclk,min_mclk > > move common related code to amd_powerplay.c > > Change-Id: Ie06c122199b7246f5b1951c354cf502bbed27485 > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> > --- > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 40 > +++++++++++++++++++++- > drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 24 +------------ > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 25 +------------- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 25 +------------ > - > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +- > 5 files changed, 44 insertions(+), 73 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > index f73e80c..310f34a 100644 > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > @@ -30,7 +30,7 @@ > #include "pp_instance.h" > #include "power_state.h" > #include "eventmanager.h" > - > +#include "eventtasks.h" > > static inline int pp_check(struct pp_instance *handle) > { > @@ -324,12 +324,44 @@ static int pp_dpm_fw_loading_complete(void > *handle) > return 0; > } > > +static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, > + enum > amd_dpm_forced_level level) > +{ > + uint32_t profile_mode_mask = > AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | > + > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | > + > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | > + > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; > + > + if (!(hwmgr->dpm_level & profile_mode_mask)) { > + /* enter umd pstate, save current level, disable gfx cg*/ > + if (level & profile_mode_mask) { > + hwmgr->saved_dpm_level = hwmgr->dpm_level; > + hwmgr->en_umd_pstate = true; > + cgs_set_clockgating_state(hwmgr->device, > + AMD_IP_BLOCK_TYPE_GFX, > + AMD_CG_STATE_UNGATE); > + } > + } else { > + /* exit umd pstate, restore level, enable gfx cg*/ > + if (!(level & profile_mode_mask)) { > + if (level == > AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) > + level = hwmgr->saved_dpm_level; > + hwmgr->en_umd_pstate = false; > + cgs_set_clockgating_state(hwmgr->device, > + AMD_IP_BLOCK_TYPE_GFX, > + AMD_CG_STATE_GATE); > + } > + } > + return; Can drop the return here. With that fixed: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > +} > + > static int pp_dpm_force_performance_level(void *handle, > enum amd_dpm_forced_level level) > { > struct pp_hwmgr *hwmgr; > struct pp_instance *pp_handle = (struct pp_instance *)handle; > int ret = 0; > + struct pem_event_data data = { {0} }; > > ret = pp_check(pp_handle); > > @@ -338,13 +370,19 @@ static int pp_dpm_force_performance_level(void > *handle, > > hwmgr = pp_handle->hwmgr; > > + if (level == hwmgr->dpm_level) > + return 0; > + > if (hwmgr->hwmgr_func->force_dpm_level == NULL) { > pr_info("%s was not implemented.\n", __func__); > return 0; > } > > mutex_lock(&pp_handle->pp_lock); > + pp_dpm_en_umd_pstate(hwmgr, level); > + pem_task_adjust_power_state(pp_handle->eventmgr, &data); > hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); > + > mutex_unlock(&pp_handle->pp_lock); > return 0; > } > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > index bc839ff..a125e30 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > @@ -1355,31 +1355,9 @@ static int cz_dpm_force_dpm_level(struct > pp_hwmgr *hwmgr, > { > uint32_t sclk = 0; > int ret = 0; > - uint32_t profile_mode_mask = > AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | > - > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | > - > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; > > if (level == hwmgr->dpm_level) > - return ret; > - > - if (!(hwmgr->dpm_level & profile_mode_mask)) { > - /* enter profile mode, save current level, disable gfx cg*/ > - if (level & profile_mode_mask) { > - hwmgr->saved_dpm_level = hwmgr->dpm_level; > - cgs_set_clockgating_state(hwmgr->device, > - AMD_IP_BLOCK_TYPE_GFX, > - AMD_CG_STATE_UNGATE); > - } > - } else { > - /* exit profile mode, restore level, enable gfx cg*/ > - if (!(level & profile_mode_mask)) { > - if (level == > AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) > - level = hwmgr->saved_dpm_level; > - cgs_set_clockgating_state(hwmgr->device, > - AMD_IP_BLOCK_TYPE_GFX, > - AMD_CG_STATE_GATE); > - } > - } > + return 0; > > switch (level) { > case AMD_DPM_FORCED_LEVEL_HIGH: > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > index f7aa057..a917fc5 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > @@ -2577,32 +2577,9 @@ static int smu7_force_dpm_level(struct > pp_hwmgr *hwmgr, > uint32_t sclk_mask = 0; > uint32_t mclk_mask = 0; > uint32_t pcie_mask = 0; > - uint32_t profile_mode_mask = > AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | > - > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | > - > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | > - > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; > > if (level == hwmgr->dpm_level) > - return ret; > - > - if (!(hwmgr->dpm_level & profile_mode_mask)) { > - /* enter profile mode, save current level, disable gfx cg*/ > - if (level & profile_mode_mask) { > - hwmgr->saved_dpm_level = hwmgr->dpm_level; > - cgs_set_clockgating_state(hwmgr->device, > - AMD_IP_BLOCK_TYPE_GFX, > - AMD_CG_STATE_UNGATE); > - } > - } else { > - /* exit profile mode, restore level, enable gfx cg*/ > - if (!(level & profile_mode_mask)) { > - if (level == > AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) > - level = hwmgr->saved_dpm_level; > - cgs_set_clockgating_state(hwmgr->device, > - AMD_IP_BLOCK_TYPE_GFX, > - AMD_CG_STATE_GATE); > - } > - } > + return 0; > > switch (level) { > case AMD_DPM_FORCED_LEVEL_HIGH: > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index 268fa24..f14047d 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -4536,32 +4536,9 @@ static int vega10_dpm_force_dpm_level(struct > pp_hwmgr *hwmgr, > uint32_t sclk_mask = 0; > uint32_t mclk_mask = 0; > uint32_t soc_mask = 0; > - uint32_t profile_mode_mask = > AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | > - > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | > - > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | > - > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; > > if (level == hwmgr->dpm_level) > - return ret; > - > - if (!(hwmgr->dpm_level & profile_mode_mask)) { > - /* enter profile mode, save current level, disable gfx cg*/ > - if (level & profile_mode_mask) { > - hwmgr->saved_dpm_level = hwmgr->dpm_level; > - cgs_set_clockgating_state(hwmgr->device, > - AMD_IP_BLOCK_TYPE_GFX, > - AMD_CG_STATE_UNGATE); > - } > - } else { > - /* exit profile mode, restore level, enable gfx cg*/ > - if (!(level & profile_mode_mask)) { > - if (level == > AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) > - level = hwmgr->saved_dpm_level; > - cgs_set_clockgating_state(hwmgr->device, > - AMD_IP_BLOCK_TYPE_GFX, > - AMD_CG_STATE_GATE); > - } > - } > + return 0; > > switch (level) { > case AMD_DPM_FORCED_LEVEL_HIGH: > diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > index eb2e277..d2224ed 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > @@ -802,12 +802,13 @@ struct pp_hwmgr { > struct amd_pp_display_configuration display_config; > uint32_t feature_mask; > > - /* power profile */ > + /* UMD Pstate */ > struct amd_pp_profile gfx_power_profile; > struct amd_pp_profile compute_power_profile; > struct amd_pp_profile default_gfx_power_profile; > struct amd_pp_profile default_compute_power_profile; > enum amd_pp_profile_type current_power_profile; > + bool en_umd_pstate; > }; > > extern int hwmgr_early_init(struct pp_instance *handle); > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
