On Tue, Aug 15, 2017 at 5:53 AM, Huang Rui <ray.huang at amd.com> wrote:
> From: Ken Wang <Ken.Wang at amd.com>
>
Please include a better description. Something like "this register
has no default value and needs to be initialized by the driver."
> Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
> Signed-off-by: Ken Wang <Ken.Wang at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 68a0d40..66312d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1670,6 +1670,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
> u32 tmp;
> u32 rb_bufsz;
> u64 rb_addr, rptr_addr, wptr_gpu_addr;
> + int r;
>
> /* Set the write pointer delay */
> WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
> @@ -1729,6 +1730,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
>
> /* start the ring */
> gfx_v9_0_cp_gfx_start(adev);
> +
> + r = amdgpu_ring_alloc(ring, 3);
> + if (r) {
> + return r;
> + }
> + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> + tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
Why the 2 << 28? What is that for?
> + amdgpu_ring_write(ring, tmp);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_commit(ring);
> +
Please either add this to the existing packet sequence in
gfx_v9_0_cp_gfx_start() or update the register via mmio in
gfx_v9_0_gpu_init().
Alex
> ring->ready = true;
>
> return 0;
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
