Am 15.08.2017 um 10:42 schrieb Christian König:
> Only two nit picks, the first one is that we need a better commit
> message.
>
> Something like: "This adds the fragment_size in the vm_manager
> structure and implements hardware setup for it."
>
> For the second see below.
>
> Am 15.08.2017 um 10:35 schrieb Roger He:
>> Change-Id: If8de884538b8eca2214f21242925d854e16e63b7
>> Signed-off-by: Roger He <Hongbo.He at amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 +----
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +-----
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +++--
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 9 ++++++---
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 9 ++++++---
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 5 +++--
>> 9 files changed, 33 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> index 4a6407d..b850bf92 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> @@ -590,11 +590,8 @@ static int amdgpu_info_ioctl(struct drm_device
>> *dev, void *data, struct drm_file
>> dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
>> dev_info.virtual_address_max =
>> (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
>> dev_info.virtual_address_alignment = max((int)PAGE_SIZE,
>> AMDGPU_GPU_PAGE_SIZE);
>> - dev_info.pte_fragment_size =
>> - (1 << AMDGPU_LOG2_PAGES_PER_FRAG(adev)) *
>> - AMDGPU_GPU_PAGE_SIZE;
>> + dev_info.pte_fragment_size = (1 <<
>> adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
>> dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
>> -
>> dev_info.cu_active_number = adev->gfx.cu_info.number;
>> dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
>> dev_info.ce_ram_size = adev->gfx.ce_ram_size;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 4b964f5..4ad04cd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -1419,9 +1419,7 @@ static int amdgpu_vm_frag_ptes(struct
>> amdgpu_pte_update_params *params,
>> * Userspace can support this by aligning virtual base address and
>> * allocation size to the fragment size.
>> */
>> -
>> - /* SI and newer are optimized for 64KB */
>> - unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev);
>> + unsigned pages_per_frag = params->adev->vm_manager.fragment_size;
>> uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);
>> uint64_t frag_align = 1 << pages_per_frag;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index 6e94cd2..d426384 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -50,11 +50,6 @@ struct amdgpu_bo_list_entry;
>> /* PTBs (Page Table Blocks) need to be aligned to 32K */
>> #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
>> -/* LOG2 number of continuous pages for the fragment field */
>> -#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \
>> - ((adev)->asic_type < CHIP_VEGA10 ? 4 : \
>> - (adev)->vm_manager.block_size)
>> -
>> #define AMDGPU_PTE_VALID (1ULL << 0)
>> #define AMDGPU_PTE_SYSTEM (1ULL << 1)
>> #define AMDGPU_PTE_SNOOPED (1ULL << 2)
>> @@ -191,6 +186,7 @@ struct amdgpu_vm_manager {
>> uint32_t num_level;
>> uint64_t vm_size;
>> uint32_t block_size;
>> + uint32_t fragment_size;
>> /* vram base address for page table entry */
>> u64 vram_base_offset;
>> /* vm pte handling */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index 6c8040e..4f2788b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct
>> amdgpu_device *adev)
>> static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>> {
>> - uint32_t tmp;
>> + uint32_t tmp, field;
>> /* Setup L2 cache */
>> tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
>> @@ -143,8 +143,9 @@ static void gfxhub_v1_0_init_cache_regs(struct
>> amdgpu_device *adev)
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>> WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
>> + field = adev->vm_manager.fragment_size;
>> tmp = mmVM_L2_CNTL3_DEFAULT;
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
>> WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index ab0a104..dcb053f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -461,6 +461,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device
>> *adev, bool enable)
>> static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
>> {
>> int r, i;
>> + u32 field;
>> if (adev->gart.robj == NULL) {
>> dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>> @@ -488,10 +489,12 @@ static int gmc_v6_0_gart_enable(struct
>> amdgpu_device *adev)
>> WREG32(mmVM_L2_CNTL2,
>> VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
>> VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
>> +
>> + field = adev->vm_manager.fragment_size;
>> WREG32(mmVM_L2_CNTL3,
>> VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
>> - (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
>> - (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
>> + (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
>> + (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
>> /* setup context0 */
>> WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start
>> >> 12);
>> WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >>
>> 12);
>> @@ -812,6 +815,7 @@ static int gmc_v6_0_sw_init(void *handle)
>> return r;
>> amdgpu_vm_adjust_size(adev, 64);
>> + adev->vm_manager.fragment_size = 4;
>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>> adev->mc.mc_mask = 0xffffffffffULL;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index 788e65e..2ac9afa 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -562,7 +562,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device
>> *adev, bool enable)
>> static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
>> {
>> int r, i;
>> - u32 tmp;
>> + u32 tmp, field;
>> if (adev->gart.robj == NULL) {
>> dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>> @@ -592,10 +592,12 @@ static int gmc_v7_0_gart_enable(struct
>> amdgpu_device *adev)
>> tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>> WREG32(mmVM_L2_CNTL2, tmp);
>> +
>> + field = adev->vm_manager.fragment_size;
>> tmp = RREG32(mmVM_L2_CNTL3);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_ASSOCIATIVITY, 1);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_FRAGMENT_SIZE, field);
>> WREG32(mmVM_L2_CNTL3, tmp);
>> /* setup context0 */
>> WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start
>> >> 12);
>> @@ -949,6 +951,7 @@ static int gmc_v7_0_sw_init(void *handle)
>> * Max GPUVM size for cayman and SI is 40 bits.
>> */
>> amdgpu_vm_adjust_size(adev, 64);
>> + adev->vm_manager.fragment_size = 4;
>
> I knew that this gets removed with the next patch, but just to avoid
> breaking bisecting, use "adev->asic_type < CHIP_VEGA10 ? 4 : 9" here.
My fault, just seen that this is GFX7 specific code. So just forget this
comment.
Christian.
>
>
> With that fixed the patch is Reviewed-by: Christian König
> <christian.koenig at amd.com>.
>
> Regards,
> Christian.
>
>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>> /* Set the internal MC address mask
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index 8e20e50..27c70d8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -762,7 +762,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device
>> *adev, bool enable)
>> static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
>> {
>> int r, i;
>> - u32 tmp;
>> + u32 tmp, field;
>> if (adev->gart.robj == NULL) {
>> dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>> @@ -793,10 +793,12 @@ static int gmc_v8_0_gart_enable(struct
>> amdgpu_device *adev)
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>> WREG32(mmVM_L2_CNTL2, tmp);
>> +
>> + field = adev->vm_manager.fragment_size;
>> tmp = RREG32(mmVM_L2_CNTL3);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_ASSOCIATIVITY, 1);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_FRAGMENT_SIZE, field);
>> WREG32(mmVM_L2_CNTL3, tmp);
>> /* XXX: set to enable PTE/PDE in system memory */
>> tmp = RREG32(mmVM_L2_CNTL4);
>> @@ -1047,6 +1049,7 @@ static int gmc_v8_0_sw_init(void *handle)
>> * Max GPUVM size for cayman and SI is 40 bits.
>> */
>> amdgpu_vm_adjust_size(adev, 64);
>> + adev->vm_manager.fragment_size = 4;
>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>> /* Set the internal MC address mask
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index c22899a..f721b4f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -541,10 +541,12 @@ static int gmc_v9_0_sw_init(void *handle)
>> adev->vm_manager.vm_size = 1U << 18;
>> adev->vm_manager.block_size = 9;
>> adev->vm_manager.num_level = 3;
>> + adev->vm_manager.fragment_size = 9;
>> } else {
>> /* vm_size is 64GB for legacy 2-level page support*/
>> amdgpu_vm_adjust_size(adev, 64);
>> adev->vm_manager.num_level = 1;
>> + adev->vm_manager.fragment_size = 9;
>> }
>> break;
>> case CHIP_VEGA10:
>> @@ -558,14 +560,16 @@ static int gmc_v9_0_sw_init(void *handle)
>> adev->vm_manager.vm_size = 1U << 18;
>> adev->vm_manager.block_size = 9;
>> adev->vm_manager.num_level = 3;
>> + adev->vm_manager.fragment_size = 9;
>> break;
>> default:
>> break;
>> }
>> - DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
>> + DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size
>> is %u-bit\n",
>> adev->vm_manager.vm_size,
>> - adev->vm_manager.block_size);
>> + adev->vm_manager.block_size,
>> + adev->vm_manager.fragment_size);
>> /* This interrupt is VMC page fault.*/
>> r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> index 74cb647..4395a4f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> @@ -138,7 +138,7 @@ static void mmhub_v1_0_init_tlb_regs(struct
>> amdgpu_device *adev)
>> static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>> {
>> - uint32_t tmp;
>> + uint32_t tmp, field;
>> /* Setup L2 cache */
>> tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
>> @@ -157,8 +157,9 @@ static void mmhub_v1_0_init_cache_regs(struct
>> amdgpu_device *adev)
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
>> + field = adev->vm_manager.fragment_size;
>> tmp = mmVM_L2_CNTL3_DEFAULT;
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
>> L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
>> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
>
>
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