[PATCH 071/120] drm/amd/display: Keep blank until set visibility to true after mode switch

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From: Yongqiang Sun <yongqiang.sun@xxxxxxx>

Change-Id: Ic399c4d985189a0c6ecc0e0447d8b2348692bbed
Signed-off-by: Yongqiang Sun <yongqiang.sun at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c       | 21 +++++++++------------
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c |  4 ++++
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 83b8b196cc1e..ba8093317aa9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1609,12 +1609,10 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 			if (!pipe_ctx->surface || pipe_ctx->top_pipe)
 				continue;
 
-			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
-				core_dc->hwss.pipe_control_lock(
-						core_dc,
-						pipe_ctx,
-						true);
-			}
+			core_dc->hwss.pipe_control_lock(
+					core_dc,
+					pipe_ctx,
+					true);
 		}
 		if (update_type == UPDATE_TYPE_FULL)
 			break;
@@ -1697,12 +1695,11 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 			if (!pipe_ctx->surface || pipe_ctx->top_pipe)
 				continue;
 
-			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
-				core_dc->hwss.pipe_control_lock(
-						core_dc,
-						pipe_ctx,
-						false);
-			}
+			core_dc->hwss.pipe_control_lock(
+					core_dc,
+					pipe_ctx,
+					false);
+
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index a8c254f66c98..c46b3e82cdcc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -52,6 +52,10 @@ void dce_pipe_control_lock(struct core_dc *dc,
 	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
 	struct dce_hwseq *hws = dc->hwseq;
 
+	/* Not lock pipe when blank */
+	if (lock && pipe->tg->funcs->is_blanked(pipe->tg))
+		return;
+
 	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
 			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
 			BLND_SCL_V_UPDATE_LOCK, &scl,
-- 
2.11.0



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