> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Friday, April 28, 2017 1:20 AM > To: amd-gfx at lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 3/3] drm/amd/powerplay: implement stop dpm task for > vega10. > > Change-Id: I19202f1e54ce6a1b8b54aacbc0d42dbba7605662 > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> Series is: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 97 > ++++++++++++++++++++++ > .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 23 +++++ > .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 1 + > .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 2 +- > .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 + > 5 files changed, 123 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index 5e3e89b..68eae52 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -2420,6 +2420,26 @@ static int > vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) > return 0; > } > > +static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) > +{ > + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr- > >backend); > + > + if (data->smu_features[GNLD_THERMAL].supported) { > + if (!data->smu_features[GNLD_THERMAL].enabled) > + pr_info("THERMAL Feature Already disabled!"); > + > + PP_ASSERT_WITH_CODE( > + !vega10_enable_smc_features(hwmgr- > >smumgr, > + false, > + data- > >smu_features[GNLD_THERMAL].smu_feature_bitmap), > + "disable THERMAL Feature Failed!", > + return -1); > + data->smu_features[GNLD_THERMAL].enabled = false; > + } > + > + return 0; > +} > + > static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) > { > struct vega10_hwmgr *data = > @@ -2498,6 +2518,37 @@ static int > vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) > return 0; > } > > +static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) > +{ > + struct vega10_hwmgr *data = > + (struct vega10_hwmgr *)(hwmgr->backend); > + uint32_t i, feature_mask = 0; > + > + > + if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ > + > PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr- > >smumgr, > + true, data- > >smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), > + "Attempt to Enable LED DPM feature Failed!", return - > EINVAL); > + data->smu_features[GNLD_LED_DISPLAY].enabled = true; > + } > + > + for (i = 0; i < GNLD_DPM_MAX; i++) { > + if (data->smu_features[i].smu_feature_bitmap & bitmap) { > + if (data->smu_features[i].supported) { > + if (data->smu_features[i].enabled) { > + feature_mask |= data- > >smu_features[i]. > + > smu_feature_bitmap; > + data->smu_features[i].enabled = > false; > + } > + } > + } > + } > + > + vega10_enable_smc_features(hwmgr->smumgr, false, > feature_mask); > + > + return 0; > +} > + > /** > * @brief Tell SMC to enabled the supported DPMs. > * > @@ -4356,11 +4407,55 @@ static int vega10_check_states_equal(struct > pp_hwmgr *hwmgr, > return is_update_required; > } > > +static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) > +{ > + int tmp_result, result = 0; > + > + tmp_result = (vega10_is_dpm_running(hwmgr)) ? 0 : -1; > + PP_ASSERT_WITH_CODE(tmp_result == 0, > + "DPM is not running right now, no need to disable > DPM!", > + return 0); > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_ThermalController)) > + vega10_disable_thermal_protection(hwmgr); > + > + tmp_result = vega10_disable_power_containment(hwmgr); > + PP_ASSERT_WITH_CODE((tmp_result == 0), > + "Failed to disable power containment!", result = > tmp_result); > + > + tmp_result = vega10_avfs_enable(hwmgr, false); > + PP_ASSERT_WITH_CODE((tmp_result == 0), > + "Failed to disable AVFS!", result = tmp_result); > + > + tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); > + PP_ASSERT_WITH_CODE((tmp_result == 0), > + "Failed to stop DPM!", result = tmp_result); > + > + return result; > +} > + > +static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) > +{ > + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr- > >backend); > + int result; > + > + result = vega10_disable_dpm_tasks(hwmgr); > + PP_ASSERT_WITH_CODE((0 == result), > + "[disable_dpm_tasks] Failed to disable DPM!", > + ); > + data->water_marks_bitmap &= ~(WaterMarksLoaded); > + > + return result; > +} > + > + > static const struct pp_hwmgr_func vega10_hwmgr_funcs = { > .backend_init = vega10_hwmgr_backend_init, > .backend_fini = vega10_hwmgr_backend_fini, > .asic_setup = vega10_setup_asic_task, > .dynamic_state_management_enable = vega10_enable_dpm_tasks, > + .dynamic_state_management_disable = vega10_disable_dpm_tasks, > .get_num_of_pp_table_entries = > vega10_get_number_of_powerplay_table_entries, > .get_power_state_size = vega10_get_power_state_size, > @@ -4400,6 +4495,8 @@ static int vega10_check_states_equal(struct > pp_hwmgr *hwmgr, > .check_states_equal = vega10_check_states_equal, > .check_smc_update_required_for_display_configuration = > > vega10_check_smc_update_required_for_display_configuration, > + .power_off_asic = vega10_power_off_asic, > + .disable_smc_firmware_ctf = vega10_thermal_disable_alert, > }; > > int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > index f1e244c..692f752 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c > @@ -113,6 +113,29 @@ int vega10_enable_power_containment(struct > pp_hwmgr *hwmgr) > return result; > } > > +int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) > +{ > + struct vega10_hwmgr *data = > + (struct vega10_hwmgr *)(hwmgr->backend); > + > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_PowerContainment)) { > + if (data->smu_features[GNLD_PPT].supported) > + > PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr- > >smumgr, > + false, data- > >smu_features[GNLD_PPT].smu_feature_bitmap), > + "Attempt to disable PPT feature > Failed!", > + data- > >smu_features[GNLD_PPT].supported = false); > + > + if (data->smu_features[GNLD_TDC].supported) > + > PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr- > >smumgr, > + false, data- > >smu_features[GNLD_TDC].smu_feature_bitmap), > + "Attempt to disable PPT feature > Failed!", > + data- > >smu_features[GNLD_TDC].supported = false); > + } > + > + return 0; > +} > + > static int vega10_set_overdrive_target_percentage(struct pp_hwmgr > *hwmgr, > uint32_t adjust_percent) > { > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > index d9662bf..9ecaa27 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h > @@ -60,6 +60,7 @@ struct vega10_pt_defaults { > int vega10_enable_power_containment(struct pp_hwmgr *hwmgr); > int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); > int vega10_power_control_set_level(struct pp_hwmgr *hwmgr); > +int vega10_disable_power_containment(struct pp_hwmgr *hwmgr); > > #endif /* _VEGA10_POWERTUNE_H_ */ > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c > index f4d77b6..7062ec8 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c > @@ -501,7 +501,7 @@ static int vega10_thermal_enable_alert(struct > pp_hwmgr *hwmgr) > * Disable thermal alerts on the RV770 thermal controller. > * @param hwmgr The address of the hardware manager. > */ > -static int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) > +int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) > { > struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr- > >backend); > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h > index 8036808..70c1d22 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h > @@ -78,6 +78,7 @@ extern int vega10_fan_ctrl_get_fan_speed_rpm(struct > pp_hwmgr *hwmgr, > uint32_t *speed); > extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr > *hwmgr); > extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr); > +extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr); > > #endif > > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
