Am 26.04.2017 um 18:36 schrieb Deucher, Alexander: >> -----Original Message----- >> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf >> Of Christian König >> Sent: Wednesday, April 26, 2017 9:14 AM >> To: amd-gfx at lists.freedesktop.org >> Subject: [PATCH] drm/amdgpu: remove unused and mostly unimplemented >> CGS functions >> >> From: Christian König <christian.koenig at amd.com> >> >> Those functions are all unused and some not even implemented. >> >> Signed-off-by: Christian König <christian.koenig at amd.com> > I think some of this is used by the ACP driver (cgs_get_pci_resource for example). Make sure that is enabled in your build. You might also want to check with Felix for KFD. Good point. I was only searching outside of the amdgpu subdirectory for users. Why is a file which is part of amdgpu even using this? v2 is on the list. Christian. > > Alex > >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 233 ------------------------ >> drivers/gpu/drm/amd/include/cgs_common.h | 303 ----------------------------- >> -- >> 2 files changed, 536 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c >> index a1a2d44..93f5dcc 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c >> @@ -42,82 +42,6 @@ struct amdgpu_cgs_device { >> struct amdgpu_device *adev = \ >> ((struct amdgpu_cgs_device *)cgs_device)->adev >> >> -static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum >> cgs_gpu_mem_type type, >> - uint64_t *mc_start, uint64_t *mc_size, >> - uint64_t *mem_size) >> -{ >> - CGS_FUNC_ADEV; >> - switch(type) { >> - case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB: >> - case CGS_GPU_MEM_TYPE__VISIBLE_FB: >> - *mc_start = 0; >> - *mc_size = adev->mc.visible_vram_size; >> - *mem_size = adev->mc.visible_vram_size - adev- >>> vram_pin_size; >> - break; >> - case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: >> - case CGS_GPU_MEM_TYPE__INVISIBLE_FB: >> - *mc_start = adev->mc.visible_vram_size; >> - *mc_size = adev->mc.real_vram_size - adev- >>> mc.visible_vram_size; >> - *mem_size = *mc_size; >> - break; >> - case CGS_GPU_MEM_TYPE__GART_CACHEABLE: >> - case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE: >> - *mc_start = adev->mc.gtt_start; >> - *mc_size = adev->mc.gtt_size; >> - *mem_size = adev->mc.gtt_size - adev->gart_pin_size; >> - break; >> - default: >> - return -EINVAL; >> - } >> - >> - return 0; >> -} >> - >> -static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void >> *kmem, >> - uint64_t size, >> - uint64_t min_offset, uint64_t max_offset, >> - cgs_handle_t *kmem_handle, uint64_t >> *mcaddr) >> -{ >> - CGS_FUNC_ADEV; >> - int ret; >> - struct amdgpu_bo *bo; >> - struct page *kmem_page = vmalloc_to_page(kmem); >> - int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT; >> - >> - struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, >> npages); >> - ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false, >> - AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, >> &bo); >> - if (ret) >> - return ret; >> - ret = amdgpu_bo_reserve(bo, false); >> - if (unlikely(ret != 0)) >> - return ret; >> - >> - /* pin buffer into GTT */ >> - ret = amdgpu_bo_pin_restricted(bo, >> AMDGPU_GEM_DOMAIN_GTT, >> - min_offset, max_offset, mcaddr); >> - amdgpu_bo_unreserve(bo); >> - >> - *kmem_handle = (cgs_handle_t)bo; >> - return ret; >> -} >> - >> -static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, >> cgs_handle_t kmem_handle) >> -{ >> - struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle; >> - >> - if (obj) { >> - int r = amdgpu_bo_reserve(obj, false); >> - if (likely(r == 0)) { >> - amdgpu_bo_unpin(obj); >> - amdgpu_bo_unreserve(obj); >> - } >> - amdgpu_bo_unref(&obj); >> - >> - } >> - return 0; >> -} >> - >> static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, >> enum cgs_gpu_mem_type type, >> uint64_t size, uint64_t align, >> @@ -349,96 +273,6 @@ static void amdgpu_cgs_write_ind_register(struct >> cgs_device *cgs_device, >> WARN(1, "Invalid indirect register space"); >> } >> >> -static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device >> *cgs_device, unsigned addr) >> -{ >> - CGS_FUNC_ADEV; >> - uint8_t val; >> - int ret = pci_read_config_byte(adev->pdev, addr, &val); >> - if (WARN(ret, "pci_read_config_byte error")) >> - return 0; >> - return val; >> -} >> - >> -static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device >> *cgs_device, unsigned addr) >> -{ >> - CGS_FUNC_ADEV; >> - uint16_t val; >> - int ret = pci_read_config_word(adev->pdev, addr, &val); >> - if (WARN(ret, "pci_read_config_word error")) >> - return 0; >> - return val; >> -} >> - >> -static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device >> *cgs_device, >> - unsigned addr) >> -{ >> - CGS_FUNC_ADEV; >> - uint32_t val; >> - int ret = pci_read_config_dword(adev->pdev, addr, &val); >> - if (WARN(ret, "pci_read_config_dword error")) >> - return 0; >> - return val; >> -} >> - >> -static void amdgpu_cgs_write_pci_config_byte(struct cgs_device >> *cgs_device, unsigned addr, >> - uint8_t value) >> -{ >> - CGS_FUNC_ADEV; >> - int ret = pci_write_config_byte(adev->pdev, addr, value); >> - WARN(ret, "pci_write_config_byte error"); >> -} >> - >> -static void amdgpu_cgs_write_pci_config_word(struct cgs_device >> *cgs_device, unsigned addr, >> - uint16_t value) >> -{ >> - CGS_FUNC_ADEV; >> - int ret = pci_write_config_word(adev->pdev, addr, value); >> - WARN(ret, "pci_write_config_word error"); >> -} >> - >> -static void amdgpu_cgs_write_pci_config_dword(struct cgs_device >> *cgs_device, unsigned addr, >> - uint32_t value) >> -{ >> - CGS_FUNC_ADEV; >> - int ret = pci_write_config_dword(adev->pdev, addr, value); >> - WARN(ret, "pci_write_config_dword error"); >> -} >> - >> - >> -static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, >> - enum cgs_resource_type resource_type, >> - uint64_t size, >> - uint64_t offset, >> - uint64_t *resource_base) >> -{ >> - CGS_FUNC_ADEV; >> - >> - if (resource_base == NULL) >> - return -EINVAL; >> - >> - switch (resource_type) { >> - case CGS_RESOURCE_TYPE_MMIO: >> - if (adev->rmmio_size == 0) >> - return -ENOENT; >> - if ((offset + size) > adev->rmmio_size) >> - return -EINVAL; >> - *resource_base = adev->rmmio_base; >> - return 0; >> - case CGS_RESOURCE_TYPE_DOORBELL: >> - if (adev->doorbell.size == 0) >> - return -ENOENT; >> - if ((offset + size) > adev->doorbell.size) >> - return -EINVAL; >> - *resource_base = adev->doorbell.base; >> - return 0; >> - case CGS_RESOURCE_TYPE_FB: >> - case CGS_RESOURCE_TYPE_IO: >> - case CGS_RESOURCE_TYPE_ROM: >> - default: >> - return -EINVAL; >> - } >> -} >> - >> static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device >> *cgs_device, >> unsigned table, uint16_t >> *size, >> uint8_t *frev, uint8_t *crev) >> @@ -477,56 +311,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct >> cgs_device *cgs_device, unsigne >> adev->mode_info.atom_context, table, args); >> } >> >> -static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, >> cgs_handle_t *request) >> -{ >> - /* TODO */ >> - return 0; >> -} >> - >> -static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, >> cgs_handle_t request) >> -{ >> - /* TODO */ >> - return 0; >> -} >> - >> -static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, >> cgs_handle_t request, >> - int active) >> -{ >> - /* TODO */ >> - return 0; >> -} >> - >> -static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, >> cgs_handle_t request, >> - enum cgs_clock clock, unsigned freq) >> -{ >> - /* TODO */ >> - return 0; >> -} >> - >> -static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, >> cgs_handle_t request, >> - enum cgs_engine engine, int >> powered) >> -{ >> - /* TODO */ >> - return 0; >> -} >> - >> - >> - >> -static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device >> *cgs_device, >> - enum cgs_clock clock, >> - struct cgs_clock_limits *limits) >> -{ >> - /* TODO */ >> - return 0; >> -} >> - >> -static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, >> uint32_t mask, >> - const uint32_t *voltages) >> -{ >> - DRM_ERROR("not implemented"); >> - return -EPERM; >> -} >> - >> struct cgs_irq_params { >> unsigned src_id; >> cgs_irq_source_set_func_t set; >> @@ -1278,9 +1062,6 @@ static int amdgpu_cgs_call_acpi_method(struct >> cgs_device *cgs_device, >> } >> >> static const struct cgs_ops amdgpu_cgs_ops = { >> - .gpu_mem_info = amdgpu_cgs_gpu_mem_info, >> - .gmap_kmem = amdgpu_cgs_gmap_kmem, >> - .gunmap_kmem = amdgpu_cgs_gunmap_kmem, >> .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem, >> .free_gpu_mem = amdgpu_cgs_free_gpu_mem, >> .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem, >> @@ -1291,23 +1072,9 @@ static const struct cgs_ops amdgpu_cgs_ops = { >> .write_register = amdgpu_cgs_write_register, >> .read_ind_register = amdgpu_cgs_read_ind_register, >> .write_ind_register = amdgpu_cgs_write_ind_register, >> - .read_pci_config_byte = amdgpu_cgs_read_pci_config_byte, >> - .read_pci_config_word = amdgpu_cgs_read_pci_config_word, >> - .read_pci_config_dword = amdgpu_cgs_read_pci_config_dword, >> - .write_pci_config_byte = amdgpu_cgs_write_pci_config_byte, >> - .write_pci_config_word = amdgpu_cgs_write_pci_config_word, >> - .write_pci_config_dword = amdgpu_cgs_write_pci_config_dword, >> - .get_pci_resource = amdgpu_cgs_get_pci_resource, >> .atom_get_data_table = amdgpu_cgs_atom_get_data_table, >> .atom_get_cmd_table_revs = >> amdgpu_cgs_atom_get_cmd_table_revs, >> .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table, >> - .create_pm_request = amdgpu_cgs_create_pm_request, >> - .destroy_pm_request = amdgpu_cgs_destroy_pm_request, >> - .set_pm_request = amdgpu_cgs_set_pm_request, >> - .pm_request_clock = amdgpu_cgs_pm_request_clock, >> - .pm_request_engine = amdgpu_cgs_pm_request_engine, >> - .pm_query_clock_limits = amdgpu_cgs_pm_query_clock_limits, >> - .set_camera_voltages = amdgpu_cgs_set_camera_voltages, >> .get_firmware_info = amdgpu_cgs_get_firmware_info, >> .rel_firmware = amdgpu_cgs_rel_firmware, >> .set_powergating_state = amdgpu_cgs_set_powergating_state, >> diff --git a/drivers/gpu/drm/amd/include/cgs_common.h >> b/drivers/gpu/drm/amd/include/cgs_common.h >> index 17b9d41..7d84267 100755 >> --- a/drivers/gpu/drm/amd/include/cgs_common.h >> +++ b/drivers/gpu/drm/amd/include/cgs_common.h >> @@ -54,20 +54,6 @@ enum cgs_ind_reg { >> }; >> >> /** >> - * enum cgs_clock - Clocks controlled by the SMU >> - */ >> -enum cgs_clock { >> - CGS_CLOCK__SCLK, >> - CGS_CLOCK__MCLK, >> - CGS_CLOCK__VCLK, >> - CGS_CLOCK__DCLK, >> - CGS_CLOCK__ECLK, >> - CGS_CLOCK__ACLK, >> - CGS_CLOCK__ICLK, >> - /* ... */ >> -}; >> - >> -/** >> * enum cgs_engine - Engines that can be statically power-gated >> */ >> enum cgs_engine { >> @@ -81,15 +67,6 @@ enum cgs_engine { >> /* ... */ >> }; >> >> -/** >> - * enum cgs_voltage_planes - Voltage planes for external camera HW >> - */ >> -enum cgs_voltage_planes { >> - CGS_VOLTAGE_PLANE__SENSOR0, >> - CGS_VOLTAGE_PLANE__SENSOR1, >> - /* ... */ >> -}; >> - >> /* >> * enum cgs_ucode_id - Firmware types for different IPs >> */ >> @@ -135,28 +112,6 @@ struct cgs_system_info { >> uint64_t padding[13]; >> }; >> >> -/* >> - * enum cgs_resource_type - GPU resource type >> - */ >> -enum cgs_resource_type { >> - CGS_RESOURCE_TYPE_MMIO = 0, >> - CGS_RESOURCE_TYPE_FB, >> - CGS_RESOURCE_TYPE_IO, >> - CGS_RESOURCE_TYPE_DOORBELL, >> - CGS_RESOURCE_TYPE_ROM, >> -}; >> - >> -/** >> - * struct cgs_clock_limits - Clock limits >> - * >> - * Clocks are specified in 10KHz units. >> - */ >> -struct cgs_clock_limits { >> - unsigned min; /**< Minimum supported frequency */ >> - unsigned max; /**< Maxumim supported frequency */ >> - unsigned sustainable; /**< Thermally sustainable frequency */ >> -}; >> - >> /** >> * struct cgs_firmware_info - Firmware information >> */ >> @@ -221,54 +176,6 @@ struct cgs_acpi_method_info { >> }; >> >> /** >> - * cgs_gpu_mem_info() - Return information about memory heaps >> - * @cgs_device: opaque device handle >> - * @type: memory type >> - * @mc_start: Start MC address of the heap (output) >> - * @mc_size: MC address space size (output) >> - * @mem_size: maximum amount of memory available for allocation >> (output) >> - * >> - * This function returns information about memory heaps. The type >> - * parameter is used to select the memory heap. The mc_start and >> - * mc_size for GART heaps may be bigger than the memory available for >> - * allocation. >> - * >> - * mc_start and mc_size are undefined for non-contiguous FB memory >> - * types, since buffers allocated with these types may or may not be >> - * GART mapped. >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum >> cgs_gpu_mem_type type, >> - uint64_t *mc_start, uint64_t *mc_size, >> - uint64_t *mem_size); >> - >> -/** >> - * cgs_gmap_kmem() - map kernel memory to GART aperture >> - * @cgs_device: opaque device handle >> - * @kmem: pointer to kernel memory >> - * @size: size to map >> - * @min_offset: minimum offset from start of GART aperture >> - * @max_offset: maximum offset from start of GART aperture >> - * @kmem_handle: kernel memory handle (output) >> - * @mcaddr: MC address (output) >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void >> *kmem, uint64_t size, >> - uint64_t min_offset, uint64_t max_offset, >> - cgs_handle_t *kmem_handle, uint64_t >> *mcaddr); >> - >> -/** >> - * cgs_gunmap_kmem() - unmap kernel memory >> - * @cgs_device: opaque device handle >> - * @kmem_handle: kernel memory handle returned by gmap_kmem >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, >> cgs_handle_t kmem_handle); >> - >> -/** >> * cgs_alloc_gpu_mem() - Allocate GPU memory >> * @cgs_device: opaque device handle >> * @type: memory type >> @@ -392,78 +299,6 @@ typedef void (*cgs_write_ind_register_t)(struct >> cgs_device *cgs_device, enum cgs >> unsigned index, uint32_t value); >> >> /** >> - * cgs_read_pci_config_byte() - Read byte from PCI configuration space >> - * @cgs_device: opaque device handle >> - * @addr: address >> - * >> - * Return: Value read >> - */ >> -typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device >> *cgs_device, unsigned addr); >> - >> -/** >> - * cgs_read_pci_config_word() - Read word from PCI configuration space >> - * @cgs_device: opaque device handle >> - * @addr: address, must be word-aligned >> - * >> - * Return: Value read >> - */ >> -typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device >> *cgs_device, unsigned addr); >> - >> -/** >> - * cgs_read_pci_config_dword() - Read dword from PCI configuration space >> - * @cgs_device: opaque device handle >> - * @addr: address, must be dword-aligned >> - * >> - * Return: Value read >> - */ >> -typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device >> *cgs_device, >> - unsigned addr); >> - >> -/** >> - * cgs_write_pci_config_byte() - Write byte to PCI configuration space >> - * @cgs_device: opaque device handle >> - * @addr: address >> - * @value: value to write >> - */ >> -typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device >> *cgs_device, unsigned addr, >> - uint8_t value); >> - >> -/** >> - * cgs_write_pci_config_word() - Write byte to PCI configuration space >> - * @cgs_device: opaque device handle >> - * @addr: address, must be word-aligned >> - * @value: value to write >> - */ >> -typedef void (*cgs_write_pci_config_word_t)(struct cgs_device >> *cgs_device, unsigned addr, >> - uint16_t value); >> - >> -/** >> - * cgs_write_pci_config_dword() - Write byte to PCI configuration space >> - * @cgs_device: opaque device handle >> - * @addr: address, must be dword-aligned >> - * @value: value to write >> - */ >> -typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device >> *cgs_device, unsigned addr, >> - uint32_t value); >> - >> - >> -/** >> - * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) >> - * @cgs_device: opaque device handle >> - * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) >> - * @size: size of the region >> - * @offset: offset from the start of the region >> - * @resource_base: base address (not including offset) returned >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, >> - enum cgs_resource_type resource_type, >> - uint64_t size, >> - uint64_t offset, >> - uint64_t *resource_base); >> - >> -/** >> * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table >> * @cgs_device: opaque device handle >> * @table: data table index >> @@ -501,87 +336,6 @@ typedef int (*cgs_atom_exec_cmd_table_t)(struct >> cgs_device *cgs_device, >> unsigned table, void *args); >> >> /** >> - * cgs_create_pm_request() - Create a power management request >> - * @cgs_device: opaque device handle >> - * @request: handle of created PM request (output) >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, >> cgs_handle_t *request); >> - >> -/** >> - * cgs_destroy_pm_request() - Destroy a power management request >> - * @cgs_device: opaque device handle >> - * @request: handle of created PM request >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, >> cgs_handle_t request); >> - >> -/** >> - * cgs_set_pm_request() - Activate or deactiveate a PM request >> - * @cgs_device: opaque device handle >> - * @request: PM request handle >> - * @active: 0 = deactivate, non-0 = activate >> - * >> - * While a PM request is active, its minimum clock requests are taken >> - * into account as the requested engines are powered up. When the >> - * request is inactive, the engines may be powered down and clocks may >> - * be lower, depending on other PM requests by other driver >> - * components. >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, >> cgs_handle_t request, >> - int active); >> - >> -/** >> - * cgs_pm_request_clock() - Request a minimum frequency for a specific >> clock >> - * @cgs_device: opaque device handle >> - * @request: PM request handle >> - * @clock: which clock? >> - * @freq: requested min. frequency in 10KHz units (0 to clear request) >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, >> cgs_handle_t request, >> - enum cgs_clock clock, unsigned freq); >> - >> -/** >> - * cgs_pm_request_engine() - Request an engine to be powered up >> - * @cgs_device: opaque device handle >> - * @request: PM request handle >> - * @engine: which engine? >> - * @powered: 0 = powered down, non-0 = powered up >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, >> cgs_handle_t request, >> - enum cgs_engine engine, int powered); >> - >> -/** >> - * cgs_pm_query_clock_limits() - Query clock frequency limits >> - * @cgs_device: opaque device handle >> - * @clock: which clock? >> - * @limits: clock limits >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, >> - enum cgs_clock clock, >> - struct cgs_clock_limits *limits); >> - >> -/** >> - * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage >> planes >> - * @cgs_device: opaque device handle >> - * @mask: bitmask of voltages to change >> (1<<CGS_VOLTAGE_PLANE__xyz|...) >> - * @voltages: pointer to array of voltage values in 1mV units >> - * >> - * Return: 0 on success, -errno otherwise >> - */ >> -typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, >> uint32_t mask, >> - const uint32_t *voltages); >> -/** >> * cgs_get_firmware_info - Get the firmware information from core driver >> * @cgs_device: opaque device handle >> * @type: the firmware type >> @@ -627,9 +381,6 @@ typedef int (*cgs_enter_safe_mode)(struct >> cgs_device *cgs_device, bool en); >> >> struct cgs_ops { >> /* memory management calls (similar to KFD interface) */ >> - cgs_gpu_mem_info_t gpu_mem_info; >> - cgs_gmap_kmem_t gmap_kmem; >> - cgs_gunmap_kmem_t gunmap_kmem; >> cgs_alloc_gpu_mem_t alloc_gpu_mem; >> cgs_free_gpu_mem_t free_gpu_mem; >> cgs_gmap_gpu_mem_t gmap_gpu_mem; >> @@ -641,27 +392,10 @@ struct cgs_ops { >> cgs_write_register_t write_register; >> cgs_read_ind_register_t read_ind_register; >> cgs_write_ind_register_t write_ind_register; >> - /* PCI configuration space access */ >> - cgs_read_pci_config_byte_t read_pci_config_byte; >> - cgs_read_pci_config_word_t read_pci_config_word; >> - cgs_read_pci_config_dword_t read_pci_config_dword; >> - cgs_write_pci_config_byte_t write_pci_config_byte; >> - cgs_write_pci_config_word_t write_pci_config_word; >> - cgs_write_pci_config_dword_t write_pci_config_dword; >> - /* PCI resources */ >> - cgs_get_pci_resource_t get_pci_resource; >> /* ATOM BIOS */ >> cgs_atom_get_data_table_t atom_get_data_table; >> cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; >> cgs_atom_exec_cmd_table_t atom_exec_cmd_table; >> - /* Power management */ >> - cgs_create_pm_request_t create_pm_request; >> - cgs_destroy_pm_request_t destroy_pm_request; >> - cgs_set_pm_request_t set_pm_request; >> - cgs_pm_request_clock_t pm_request_clock; >> - cgs_pm_request_engine_t pm_request_engine; >> - cgs_pm_query_clock_limits_t pm_query_clock_limits; >> - cgs_set_camera_voltages_t set_camera_voltages; >> /* Firmware Info */ >> cgs_get_firmware_info get_firmware_info; >> cgs_rel_firmware rel_firmware; >> @@ -696,12 +430,6 @@ struct cgs_device >> #define CGS_OS_CALL(func,dev,...) \ >> (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) >> >> -#define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) >> \ >> - CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) >> -#define >> cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) >> \ >> - >> CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_ha >> ndle,mcaddr) >> -#define cgs_gunmap_kmem(dev,kmem_handle) \ >> - CGS_CALL(gunmap_kmem,dev,keme_handle) >> #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) >> \ >> >> CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,han >> dle) >> #define cgs_free_gpu_mem(dev,handle) \ >> @@ -724,19 +452,6 @@ struct cgs_device >> #define cgs_write_ind_register(dev,space,index,value) \ >> CGS_CALL(write_ind_register,dev,space,index,value) >> >> -#define cgs_read_pci_config_byte(dev,addr) \ >> - CGS_CALL(read_pci_config_byte,dev,addr) >> -#define cgs_read_pci_config_word(dev,addr) \ >> - CGS_CALL(read_pci_config_word,dev,addr) >> -#define cgs_read_pci_config_dword(dev,addr) \ >> - CGS_CALL(read_pci_config_dword,dev,addr) >> -#define cgs_write_pci_config_byte(dev,addr,value) \ >> - CGS_CALL(write_pci_config_byte,dev,addr,value) >> -#define cgs_write_pci_config_word(dev,addr,value) \ >> - CGS_CALL(write_pci_config_word,dev,addr,value) >> -#define cgs_write_pci_config_dword(dev,addr,value) \ >> - CGS_CALL(write_pci_config_dword,dev,addr,value) >> - >> #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ >> CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) >> #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ >> @@ -744,20 +459,6 @@ struct cgs_device >> #define cgs_atom_exec_cmd_table(dev,table,args) \ >> CGS_CALL(atom_exec_cmd_table,dev,table,args) >> >> -#define cgs_create_pm_request(dev,request) \ >> - CGS_CALL(create_pm_request,dev,request) >> -#define cgs_destroy_pm_request(dev,request) \ >> - CGS_CALL(destroy_pm_request,dev,request) >> -#define cgs_set_pm_request(dev,request,active) \ >> - CGS_CALL(set_pm_request,dev,request,active) >> -#define cgs_pm_request_clock(dev,request,clock,freq) \ >> - CGS_CALL(pm_request_clock,dev,request,clock,freq) >> -#define cgs_pm_request_engine(dev,request,engine,powered) \ >> - CGS_CALL(pm_request_engine,dev,request,engine,powered) >> -#define cgs_pm_query_clock_limits(dev,clock,limits) \ >> - CGS_CALL(pm_query_clock_limits,dev,clock,limits) >> -#define cgs_set_camera_voltages(dev,mask,voltages) \ >> - CGS_CALL(set_camera_voltages,dev,mask,voltages) >> #define cgs_get_firmware_info(dev, type, info) \ >> CGS_CALL(get_firmware_info, dev, type, info) >> #define cgs_rel_firmware(dev, type) \ >> @@ -776,10 +477,6 @@ struct cgs_device >> CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, >> pintput, poutput, output_count, input_size, output_size) >> #define cgs_query_system_info(dev, sys_info) \ >> CGS_CALL(query_system_info, dev, sys_info) >> -#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ >> - resource_base) \ >> - CGS_CALL(get_pci_resource, cgs_device, resource_type, size, >> offset, \ >> - resource_base) >> >> #define cgs_is_virtualization_enabled(cgs_device) \ >> CGS_CALL(is_virtualization_enabled, cgs_device) >> -- >> 2.7.4 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
