On 27/04/17 03:45 PM, Gerd Hoffmann wrote:
> Hi,
>
>>> That is done using the RADEON_TILING_SWAP_{16,32}BIT flag mentioned in
>>> another thread?
>>
>> Right.
>>
>>
>>> What about dumb bos? You've mentioned the swap flag isn't used for
>>> those. Which implies they are in little endian byte order (both gpu and
>>> cpu view).
>>
>> Right, AFAICT from looking at the code.
>
> Ok.
>
> And I also don't see an easy way to make them big endian (cpu view)
> using swapping with the existing drm interfaces, given we apply a format
> when we put the bo into use as framebuffer, not when creating it. So
> userspace can: (1) create dumb bo, (2) map bo, (3) write something bo,
> (4) create fb + attach to crtc. And at (3) we don't know the format
> yet, so we can't configure swapping accordingly.
>
> So just not using the swapping indeed looks like the only sensible
> option. Which in turn implies there is no BGRA8888 support for dumb
> bos. Hmm, I can see the problem. Userspace expectation appears to be
> that ADDFB configures a native endian framebuffer, which the driver
> simply can't do on bigendian.
... with pre-R600 GPUs.
> So, what can/should the driver do here? Throw errors for ADDFB and
> force userspace to use ADDFB2? From a design point of view the best
> option, but in the other hand I suspect that could break the xorg radeon
> driver ...
Yes, it would.
One thing we could do is provide a way for userspace to query the
effective format(s) as seen by the GPU and/or CPU.
It might also make sense for the radeon driver to set the
RADEON_TILING_SWAP_{16,32}BIT flags for dumb BOs. I wonder about the
status of apps using dumb BOs directly wrt this discussion.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
