On 04/24/2017 01:57 PM, Chunming Zhou wrote:
> It will be used for reserving vmid.
>
> Change-Id: Ib7169ea999690c8e82d0dcbccdd2d97760c0270a
> Signed-off-by: Chunming Zhou <David1.Zhou at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
> include/uapi/drm/amdgpu_drm.h | 20 ++++++++++++++++++++
> 4 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index cad589a..7004e6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -1051,6 +1051,7 @@ int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
> const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> /* KMS */
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index f804d38..eb429c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2358,3 +2358,19 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
> }
> }
> }
> +
> +int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
> +{
> + union drm_amdgpu_vm *args = data;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_fpriv *fpriv = filp->driver_priv;
> +
> + switch (args->in.op) {
> + case AMDGPU_VM_OP_RESERVE_VMID:
How do you think to add an op to release the reserved vmid as well?
Jerry
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 0f547c6..62dbace 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -247,5 +247,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
> void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
> struct amdgpu_bo_va *bo_va);
> void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);
> +int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
>
> #endif
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 56b7a2f3..5ee639b 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -51,6 +51,7 @@
> #define DRM_AMDGPU_GEM_OP 0x10
> #define DRM_AMDGPU_GEM_USERPTR 0x11
> #define DRM_AMDGPU_WAIT_FENCES 0x12
> +#define DRM_AMDGPU_VM 0x13
>
> /* hybrid specific ioctls */
> #define DRM_AMDGPU_SEM 0x5b
> @@ -71,6 +72,7 @@
> #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
> #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
> #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
> +#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
>
> /* hybrid specific ioctls */
> #define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma)
> @@ -212,6 +214,24 @@ struct drm_amdgpu_ctx_in {
> union drm_amdgpu_ctx_out out;
> };
>
> +/* vm ioctl */
> +#define AMDGPU_VM_OP_RESERVE_VMID 1
> +struct drm_amdgpu_vm_in {
> + /** AMDGPU_VM_OP_* */
> + __u32 op;
> + __u32 flags;
> +};
> +
> +struct drm_amdgpu_vm_out {
> + /** For future use, no flags defined so far */
> + __u64 flags;
> +};
> +
> +union drm_amdgpu_vm {
> + struct drm_amdgpu_vm_in in;
> + struct drm_amdgpu_vm_out out;
> +};
> +
> /* sem related */
> #define AMDGPU_SEM_OP_CREATE_SEM 1
> #define AMDGPU_SEM_OP_WAIT_SEM 2
>
