Patches 1 and 2 are Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com> Note that we're making another change to this programming sequence in the upcoming release. Conceptually the MQD represents the state of an inactive queue. So the CP_HQD_ACTIVE and DOORBELL_EN bits should be 0 in the MQD. Then the driver (or firmware in case of HIQ or KIQ runlists) can stream the register values from the MQD into the HQD registers without activating the queue prematurely. Once all is in place, the queue can be activated. This simplifies the loops even further since all registers can be handled in a single loop (except the Tonga workaround). But it may require changes elsewhere to make sure the CP_HQD_ACTIVE and DOORBELL_EN bits are always 0 in the MQD. Regards, Felix On 17-04-13 06:04 PM, Andres Rodriguez wrote: > Second part of the split of the series: > Add support for high priority scheduling in amdgpu v8 > > These patches should be close to being good enough to land. > > The first two patches are simple fixes I've ported from the ROCm branch. These > still need review. > > I've fixed all of Christian's comments for patch 04: > drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v4 > > > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
