On platforms without GPU_POWER sensors the thread reading sensors would proceed
far too quickly. So it is now rate limited to 50Hz to be consistent.
Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
src/app/top.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/app/top.c b/src/app/top.c
index 96e33ff2e1da..364180eb70f6 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -293,18 +293,24 @@ static volatile struct umr_bitfield *sensor_bits = NULL;
static void *gpu_sensor_thread(void *data)
{
struct umr_asic asic = *((struct umr_asic*)data);
- int size, rem, off, x;
+ int size, rem, off, x, power;
char fname[128];
+ struct timespec ts;
+
+ ts.tv_sec = 0;
+ ts.tv_nsec = 1000000000UL / 50; // limit to 50Hz
snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_sensors", asic.instance);
asic.fd.sensors = open(fname, O_RDWR);
while (!sensor_thread_quit) {
rem = sizeof gpu_power_data;
off = 0;
+ power = 0;
for (x = 0; sensor_bits[x].regname; ) {
switch (sensor_bits[x].start) {
case AMDGPU_PP_SENSOR_GPU_POWER:
size = 16;
+ power = 1;
break;
default:
size = 4;
@@ -316,6 +322,10 @@ static void *gpu_sensor_thread(void *data)
rem -= size;
x += size / 4;
}
+
+ // sleep for 20ms if no GPU power sensor to rate limit things a bit
+ if (!power)
+ nanosleep(&ts, NULL);
}
close(asic.fd.sensors);
return NULL;
--
2.12.0
