On Thu, Apr 6, 2017 at 2:21 AM, Andres Rodriguez <andresx7 at gmail.com> wrote:
> The CP_MEC_DOORBELL_RANGE_* and CP_PQ_STATUS.DOORBELL_ENABLE registers
> are not HQD specific.
>
> They only need to be set once if at least 1 pipe requested doorbell
> support.
>
> v2: move doorbell_enable to amdgpu_gfx instead of amdgpu_device
This patch is no longer necessary with KIQ as we only set the doorbell
range and enable bit once.
Alex
>
> Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>
> Acked-by: Christian König <christian.koenig at amd.com>
> Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 15b9675..f8a08d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1054,20 +1054,23 @@ struct amdgpu_gfx {
> const struct amdgpu_gfx_funcs *funcs;
>
> /* reset mask */
> uint32_t grbm_soft_reset;
> uint32_t srbm_soft_reset;
> bool in_reset;
> /* s3/s4 mask */
> bool in_suspend;
> /* NGG */
> struct amdgpu_ngg ngg;
> +
> + /* doorbell */
> + bool doorbell_enabled;
> };
>
> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> unsigned size, struct amdgpu_ib *ib);
> void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
> struct dma_fence *f);
> int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
> struct amdgpu_ib *ibs, struct amdgpu_job *job,
> struct dma_fence **f);
> int amdgpu_ib_pool_init(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 88b85f7..4c79fb0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4882,35 +4882,37 @@ static int gfx_v8_0_mqd_deactivate(struct amdgpu_device *adev)
> WREG32(mmCP_HQD_PQ_WPTR, 0);
> }
>
> return 0;
> }
>
> static void gfx_v8_0_enable_doorbell(struct amdgpu_device *adev, bool enable)
> {
> uint32_t tmp;
>
> - if (!enable)
> + if (!enable || adev->gfx.doorbell_enabled)
> return;
>
> if ((adev->asic_type == CHIP_CARRIZO) ||
> (adev->asic_type == CHIP_FIJI) ||
> (adev->asic_type == CHIP_STONEY) ||
> (adev->asic_type == CHIP_POLARIS11) ||
> (adev->asic_type == CHIP_POLARIS10)) {
> WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2);
> WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2);
> }
>
> tmp = RREG32(mmCP_PQ_STATUS);
> tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
> WREG32(mmCP_PQ_STATUS, tmp);
> +
> + adev->gfx.doorbell_enabled = true;
> }
>
> static int gfx_v8_0_mqd_commit(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> struct vi_mqd *mqd = ring->mqd_ptr;
>
> /* disable wptr polling */
> WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
>
> @@ -5102,20 +5104,22 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
> }
>
> done:
> return r;
> }
>
> static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
> {
> int r;
>
> + adev->gfx.doorbell_enabled = false;
> +
> if (!(adev->flags & AMD_IS_APU))
> gfx_v8_0_enable_gui_idle_interrupt(adev, false);
>
> if (!adev->pp_enabled) {
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
> /* legacy firmware loading */
> r = gfx_v8_0_cp_gfx_load_microcode(adev);
> if (r)
> return r;
>
> --
> 2.9.3
>
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> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
