Change read/set/write patterns into WREG32_FIELD15 calls. Signed-off-by: Tom St Denis <tom.stdenis at amd.com> --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 91bdafd30c84..d82b44bb550a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -188,11 +188,8 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, (u32)((u64)adev->dummy_page.addr >> 44)); - tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, - 1); - WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); + WREG32_FIELD15(MMHUB, 0, VM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); tmp = RREG32(addr); @@ -273,9 +270,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); /* Setup L2 cache */ - tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); - WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); + WREG32_FIELD15(MMHUB, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); } -- 2.12.0
