On 04/04/2017 07:02 AM, Harry Wentland wrote: > Reviewed-by: Harry Wentland <harry.wentland at amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang at amd.com> > > On 2017-04-03 04:58 PM, Alex Deucher wrote: >> vega10 is the only soc15 asic at the moment so these >> warnings are invalid, but add a default case to silence >> the warnings. >> >> Fixes: 220ab9bd1ccf: "drm/amdgpu: soc15 enable (v3)" >> Reported-by: Dan Carpenter <dan.carpenter at oracle.com> >> Signed-off-by: Alex Deucher <alexander.deucher at amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c >> b/drivers/gpu/drm/amd/amdgpu/soc15.c >> index bb14a45..758facd 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c >> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c >> @@ -106,6 +106,8 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, >> u32 reg) >> if (adev->asic_type == CHIP_VEGA10) >> nbio_pcie_id = &nbio_v6_1_pcie_index_data; >> + else >> + BUG(); >> address = nbio_pcie_id->index_offset; >> data = nbio_pcie_id->data_offset; >> @@ -125,6 +127,8 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, >> u32 reg, u32 v) >> if (adev->asic_type == CHIP_VEGA10) >> nbio_pcie_id = &nbio_v6_1_pcie_index_data; >> + else >> + BUG(); >> address = nbio_pcie_id->index_offset; >> data = nbio_pcie_id->data_offset; > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
