> -----Original Message----- > From: Andres Rodriguez [mailto:andresx7 at gmail.com] > Sent: Tuesday, April 04, 2017 4:01 PM > To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd- > gfx at lists.freedesktop.org > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet" > > This is my info in case that is useful: > > umr.version == ea8e49bb15ed > > fw.VCE == .feature==0 .firmware==0x34040300 > fw.UVD == .feature==0 .firmware==0x014f1000 > fw.MC == .feature==0 .firmware==0x00000000 > fw.ME == .feature==37 .firmware==0x00000094 > fw.PFP == .feature==37 .firmware==0x000000dc > fw.CE == .feature==37 .firmware==0x00000080 > fw.RLC == .feature==1 .firmware==0x0000010e > fw.MEC == .feature==37 .firmware==0x000002a2 > fw.MEC2 == .feature==37 .firmware==0x000002a2 > fw.SOS == .feature==0 .firmware==0x00000000 > fw.ASD == .feature==0 .firmware==0x00000000 > fw.SMC == .feature==0 .firmware==0x00170f00 > fw.SDMA0 == .feature==31 .firmware==0x00000036 > fw.SDMA1 == .feature==0 .firmware==0x00000036 > > asic.instance == 0 > > > gfx.max_shader_engines == 4 > gfx.max_tile_pipes == 8 > gfx.max_cu_per_sh == 9 > gfx.max_sh_per_se == 1 > gfx.max_backends_per_se == 2 > gfx.max_texture_channel_caches == 8 > gfx.max_gprs == 256 > gfx.max_gs_threads == 32 > gfx.max_hw_contexts == 8 > gfx.sc_prim_fifo_size_frontend == 32 > gfx.sc_prim_fifo_size_backend == 256 > gfx.sc_hiz_tile_fifo_size == 48 > gfx.sc_earlyz_tile_fifo_size == 304 > gfx.num_tile_pipes == 8 > gfx.backend_enable_mask == 255 > gfx.mem_max_burst_length_bytes == 256 > gfx.mem_row_size_in_kb == 4 > gfx.shader_engine_tile_size == 32 > gfx.num_gpus == 1 > gfx.multi_gpu_tile_size == 64 > gfx.mc_arb_ramcfg == 24738 > gfx.gb_addr_config == 570494979 > gfx.num_rbs == 8 > gfx.family = 130, Volcanic Islands > gfx.rev_id == 00000001 > gfx.external_rev_id == 00000051 > gfx.cg_flags == 003fffcd > AMD_CG_SUPPORT_GFX_MGCG > AMD_CG_SUPPORT_GFX_CGCG > AMD_CG_SUPPORT_GFX_CGLS > AMD_CG_SUPPORT_GFX_CP_LS > AMD_CG_SUPPORT_GFX_RLC_LS > AMD_CG_SUPPORT_MC_LS > AMD_CG_SUPPORT_MC_MGCG > AMD_CG_SUPPORT_SDMA_LS > AMD_CG_SUPPORT_SDMA_MGCG > AMD_CG_SUPPORT_BIF_LS > AMD_CG_SUPPORT_UVD_MGCG > AMD_CG_SUPPORT_VCE_MGCG > AMD_CG_SUPPORT_HDP_LS > AMD_CG_SUPPORT_HDP_MGCG > AMD_CG_SUPPORT_ROM_MGCG > gfx.pg_flags == 00000000 Is this the stock firmware from upstream or the stuff I pointed you to yesterday on my fdo site? Alex > > Regards, > Andres > > On 2017-04-04 03:59 PM, Tom St Denis wrote: > > I'm using the latest from all open (our internal FC24 repo). I'll fetch > > the exact later with "umr -c". > > > > Tom > > > > On Tue, Apr 4, 2017 at 3:48 PM Deucher, Alexander > <Alexander.Deucher at amd.com> > > wrote: > > > >>> -----Original Message----- > >>> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On > Behalf > >>> Of Andres Rodriguez > >>> Sent: Tuesday, April 04, 2017 3:39 PM > >>> To: StDenis, Tom; amd-gfx at lists.freedesktop.org > >>> Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES > packet" > >>> > >>> > >>> > >>> On 2017-04-04 08:27 AM, Tom St Denis wrote: > >>>> On 03/04/17 04:25 PM, Andres Rodriguez wrote: > >>>>> Commit e579f56 results in a KCQ initialization error for polaris10 > >>>>> cards. Providing the full SET_RESOURCES packet instead of the > >> truncated > >>>>> version fixes the problem. > >>>>> > >>>>> I think this patch may have been one of the stabs at fixing the KCQ > >>>>> suspend/resume errors. I *think* it may no longer be needed if that > is > >>>>> the case. > >>>>> > >>>>> Sending this mostly as an FYI to get the patch removed from the > >> 4.12-wip > >>>>> This reverts commit e579f564c333a7eaddf7e12b1b8414410c36e80f. > >>>>> --- > >>>>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++++- > >>>>> 1 file changed, 5 insertions(+), 1 deletion(-) > >>>>> > >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>> index 2d8d7bb..4c3bf51 100644 > >>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>> @@ -4647,10 +4647,14 @@ static int gfx_v8_0_kiq_kcq_enable(struct > >>>>> amdgpu_device *adev) > >>>>> return r; > >>>>> } > >>>>> /* set resources */ > >>>>> - amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, > 2)); > >>>>> + amdgpu_ring_write(kiq_ring, > PACKET3(PACKET3_SET_RESOURCES, > >>> 6)); > >>>>> amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 > >>>>> (KIQ) */ > >>>>> amdgpu_ring_write(kiq_ring, 0x000000FF); /* queue mask lo */ > >>>>> amdgpu_ring_write(kiq_ring, 0); /* queue mask hi */ > >>>>> + amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ > >>>>> + amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ > >>>>> + amdgpu_ring_write(kiq_ring, 0); /* oac mask */ > >>>>> + amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap > >>>>> size:0 */ > >>>>> for (i = 0; i < adev->gfx.num_compute_rings; i++) { > >>>>> struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; > >>>>> uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); > >>>>> > >>>> This fixes init issues with my polaris board but there's still a clock > >>>> problem (CP is pegged at 100% as read by umr) resulting in the GPU > >> clock > >>>> staying at 1200MHz the entire time. > >>>> > >>> Yeah I sent this out because I was having KCQ init issues on my > >>> polaris10 card. However, I'm not seeing the CP pegged at 100% as you > >>> mentioned. Everything sitting quietly at 0% here. > >> Which firmware are you using? > >> > >> Alex > >> > >>> > >>>> Tom > >>>> _______________________________________________ > >>>> amd-gfx mailing list > >>>> amd-gfx at lists.freedesktop.org > >>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >>> _______________________________________________ > >>> amd-gfx mailing list > >>> amd-gfx at lists.freedesktop.org > >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >> _______________________________________________ > >> amd-gfx mailing list > >> amd-gfx at lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >>
