Am 03.04.2017 um 21:31 schrieb Alex Deucher:
> On Mon, Apr 3, 2017 at 8:39 AM, Christian König <deathsimple at vodafone.de> wrote:
>> From: Christian König <christian.koenig at amd.com>
>>
>> The two hubs are just instances of the same hardware,
>> so the register bits are identical.
> Removing get_vm_protection_bits makes sense since those are limited to
> the gmc module. I'd prefer to keep get_invalidation_req since that
> protects the ip modules from a direct dependency on gmc9. We'd end up
> reimplementing this when we come to an ip module that ends up being
> used on a chip with a newer gmc. Also seems cleaner this way in my
> opinion.
In this case let's move the callback into the mc/gart function pointers.
The crux is that we need to change those settings when we improve the VM
flushing, and I really don't want to do all changes twice.
Christian.
>
> Alex
>
>> Signed-off-by: Christian König <christian.koenig at amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 --------------------------------
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 33 +++++++++++++++++++++++++++-----
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 2 ++
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 --------------------------------
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 5 +++--
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 ++-
>> 9 files changed, 39 insertions(+), 78 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index cc43fee..f6f6dcb 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -572,8 +572,6 @@ struct amdgpu_vmhub {
>> uint32_t vm_context0_cntl;
>> uint32_t vm_l2_pro_fault_status;
>> uint32_t vm_l2_pro_fault_cntl;
>> - uint32_t (*get_invalidate_req)(unsigned int vm_id);
>> - uint32_t (*get_vm_protection_bits)(void);
>> };
>>
>> /*
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index c8a1c4e..4ae5ac0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -36,6 +36,7 @@
>> #include "soc15_common.h"
>> #include "clearstate_gfx9.h"
>> #include "v9_structs.h"
>> +#include "gmc_v9_0.h"
>>
>> #define GFX9_NUM_GFX_RINGS 1
>> #define GFX9_NUM_COMPUTE_RINGS 8
>> @@ -3148,6 +3149,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned vm_id, uint64_t pd_addr)
>> {
>> int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -3157,7 +3159,6 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> gfx_v9_0_write_data_to_reg(ring, usepfp, true,
>> hub->ctx0_ptb_addr_lo32
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index dd48637..0abb128 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -299,36 +299,6 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
>> WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
>> }
>>
>> -static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)
>> -{
>> - u32 req = 0;
>> -
>> - /* invalidate using legacy mode on vm_id*/
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - PER_VMID_INVALIDATE_REQ, 1 << vm_id);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
>> -
>> - return req;
>> -}
>> -
>> -static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)
>> -{
>> - return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
>> -}
>> -
>> static int gfxhub_v1_0_early_init(void *handle)
>> {
>> return 0;
>> @@ -361,9 +331,6 @@ static int gfxhub_v1_0_sw_init(void *handle)
>> hub->vm_l2_pro_fault_cntl =
>> SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>>
>> - hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;
>> - hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits;
>> -
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 268cedb..43b429e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -75,11 +75,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>> struct amdgpu_vmhub *hub;
>> u32 tmp, reg, bits, i;
>>
>> + bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
>> +
>> switch (state) {
>> case AMDGPU_IRQ_STATE_DISABLE:
>> /* MM HUB */
>> hub = &adev->vmhub[AMDGPU_MMHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i< 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -89,7 +96,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>>
>> /* GFX HUB */
>> hub = &adev->vmhub[AMDGPU_GFXHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i < 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -100,7 +106,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>> case AMDGPU_IRQ_STATE_ENABLE:
>> /* MM HUB */
>> hub = &adev->vmhub[AMDGPU_MMHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i< 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -110,7 +115,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>>
>> /* GFX HUB */
>> hub = &adev->vmhub[AMDGPU_GFXHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i < 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -169,6 +173,25 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
>> adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
>> }
>>
>> +uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
>> +{
>> + u32 req = 0;
>> +
>> + /* invalidate using legacy mode on vm_id*/
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> + PER_VMID_INVALIDATE_REQ, 1 << vm_id);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
>> +
>> + return req;
>> +}
>> +
>> /*
>> * GART
>> * VMID 0 is the physical GPU addresses as used by the kernel.
>> @@ -198,7 +221,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &adev->vmhub[i];
>> - u32 tmp = hub->get_invalidate_req(vmid);
>> + u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
>>
>> WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> index b030ca5..ea046a8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> @@ -27,4 +27,6 @@
>> extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
>> extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
>>
>> +uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id);
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> index c1dc8c4..6cd1c55 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> @@ -317,36 +317,6 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
>> WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
>> }
>>
>> -static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vm_id)
>> -{
>> - u32 req = 0;
>> -
>> - /* invalidate using legacy mode on vm_id*/
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - PER_VMID_INVALIDATE_REQ, 1 << vm_id);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
>> -
>> - return req;
>> -}
>> -
>> -static uint32_t mmhub_v1_0_get_vm_protection_bits(void)
>> -{
>> - return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
>> -}
>> -
>> static int mmhub_v1_0_early_init(void *handle)
>> {
>> return 0;
>> @@ -379,9 +349,6 @@ static int mmhub_v1_0_sw_init(void *handle)
>> hub->vm_l2_pro_fault_cntl =
>> SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>>
>> - hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req;
>> - hub->get_vm_protection_bits = mmhub_v1_0_get_vm_protection_bits;
>> -
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index 6cfb100..e30ea26 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -39,6 +39,7 @@
>> #include "soc15_common.h"
>> #include "soc15.h"
>> #include "vega10_sdma_pkt_open.h"
>> +#include "gmc_v9_0.h"
>>
>> MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
>> MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
>> @@ -1039,6 +1040,7 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
>> static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -1048,7 +1050,6 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
>> SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> index 3457546..593b04b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> @@ -27,6 +27,7 @@
>> #include "amdgpu_uvd.h"
>> #include "soc15d.h"
>> #include "soc15_common.h"
>> +#include "gmc_v9_0.h"
>>
>> #include "vega10/soc15ip.h"
>> #include "vega10/UVD/uvd_7_0_offset.h"
>> @@ -1045,6 +1046,7 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
>> static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> uint32_t data0, data1, mask;
>> unsigned eng = ring->idx;
>> unsigned i;
>> @@ -1055,7 +1057,6 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
>> data1 = upper_32_bits(pd_addr);
>> @@ -1091,6 +1092,7 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
>> static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned int vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -1100,7 +1102,6 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
>> amdgpu_ring_write(ring,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> index ad5fd98..9c5ce91 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> @@ -31,6 +31,7 @@
>> #include "soc15d.h"
>> #include "soc15_common.h"
>> #include "mmsch_v1_0.h"
>> +#include "gmc_v9_0.h"
>>
>> #include "vega10/soc15ip.h"
>> #include "vega10/VCE/vce_4_0_offset.h"
>> @@ -985,6 +986,7 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
>> static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned int vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -994,7 +996,6 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
>> amdgpu_ring_write(ring,
>> --
>> 2.5.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
