From: Hersen Wu <hersenxs.wu@xxxxxxx> Change-Id: Ibb7e6c05aca7fc1bd699238e16a82628286b25e0 Signed-off-by: Hersen Wu <hersenxs.wu at amd.com> Reviewed-by: Zeyu Fan <Zeyu.Fan at amd.com> Acked-by: Harry Wentland <Harry.Wentland at amd.com> --- drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 6481fb2028ee..ea4778b6e6d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct( &bp_cap_info)) enc110->base.features.flags.bits.IS_HBR2_CAPABLE = bp_cap_info.DP_HBR2_CAP; + enc110->base.features.flags.bits.IS_HBR3_CAPABLE = + bp_cap_info.DP_HBR3_EN; + } + + /* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes, + * IS_HBR3_CAPABLE = 0. + */ + /* test pattern 3 support */ enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true; + /* test pattern 4 support */ + enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true; enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false; /* -- 2.9.3
