[PATCH] drm/amdgpu: rework IP block registration (v2)

[deathsimple@xxxxxxxxxxx (Christian König)]

Am 14.10.2016 um 17:48 schrieb Alex Deucher:
> This makes it easier to replace specific IP blocks on
> asics for handling virtual_dce, DAL, etc. and for building
> IP lists for hw or tables.  This also stored the status
> information in the same structure.
>
> v2: split out spelling fix into a separate patch
>      add a function to add IPs to the list
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  42 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c       |  17 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h       |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c       |  12 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 260 ++++----
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c       |  12 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  11 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        |   6 +-
>   drivers/gpu/drm/amd/amdgpu/ci_dpm.c           |   9 +
>   drivers/gpu/drm/amd/amdgpu/cik.c              | 817 +++----------------------
>   drivers/gpu/drm/amd/amdgpu/cik.h              |   2 -
>   drivers/gpu/drm/amd/amdgpu/cik_ih.c           |  11 +-
>   drivers/gpu/drm/amd/amdgpu/cik_ih.h           |   2 +-
>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c         |  11 +-
>   drivers/gpu/drm/amd/amdgpu/cik_sdma.h         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/cz_dpm.c           |   9 +
>   drivers/gpu/drm/amd/amdgpu/cz_ih.c            |  10 +-
>   drivers/gpu/drm/amd/amdgpu/cz_ih.h            |   2 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v10_0.c        |  20 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v10_0.h        |   4 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v11_0.c        |  20 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v11_0.h        |   3 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v6_0.c         |  20 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v6_0.h         |   3 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v8_0.c         |  47 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v8_0.h         |   6 +-
>   drivers/gpu/drm/amd/amdgpu/dce_virtual.c      |  10 +-
>   drivers/gpu/drm/amd/amdgpu/dce_virtual.h      |   2 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  11 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         |  38 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h         |   5 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         |  20 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h         |   3 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |  10 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c         |  20 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h         |   3 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c         |  29 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h         |   4 +-
>   drivers/gpu/drm/amd/amdgpu/iceland_ih.c       |  10 +-
>   drivers/gpu/drm/amd/amdgpu/iceland_ih.h       |   2 +-
>   drivers/gpu/drm/amd/amdgpu/kv_dpm.c           |   9 +
>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c        |  11 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h        |   2 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c        |  20 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h        |   3 +-
>   drivers/gpu/drm/amd/amdgpu/si.c               | 288 ++-------
>   drivers/gpu/drm/amd/amdgpu/si.h               |   2 -
>   drivers/gpu/drm/amd/amdgpu/si_dma.c           |  11 +-
>   drivers/gpu/drm/amd/amdgpu/si_dma.h           |   2 +-
>   drivers/gpu/drm/amd/amdgpu/si_dpm.c           |   8 +
>   drivers/gpu/drm/amd/amdgpu/si_ih.c            |  10 +-
>   drivers/gpu/drm/amd/amdgpu/si_ih.h            |   2 +-
>   drivers/gpu/drm/amd/amdgpu/tonga_ih.c         |  10 +-
>   drivers/gpu/drm/amd/amdgpu/tonga_ih.h         |   4 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c         |  11 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c         |  11 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c         |  29 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h         |   4 +-
>   drivers/gpu/drm/amd/amdgpu/vce_v2_0.c         |  11 +-
>   drivers/gpu/drm/amd/amdgpu/vce_v2_0.h         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c         |  29 +-
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.h         |   4 +-
>   drivers/gpu/drm/amd/amdgpu/vi.c               | 837 ++++----------------------
>   drivers/gpu/drm/amd/amdgpu/vi.h               |   2 -
>   69 files changed, 924 insertions(+), 1935 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index e6f86b8..1800ea1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -195,21 +195,38 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev,
>   bool amdgpu_is_idle(struct amdgpu_device *adev,
>   		    enum amd_ip_block_type block_type);
>   
> +#define AMDGPU_MAX_IP_NUM 16
> +
> +struct amdgpu_ip_block_status {
> +	bool valid;
> +	bool sw;
> +	bool hw;
> +	bool late_initialized;
> +	bool hang;
> +};
> +
>   struct amdgpu_ip_block_version {
> -	enum amd_ip_block_type type;
> -	u32 major;
> -	u32 minor;
> -	u32 rev;
> +	const enum amd_ip_block_type type;
> +	const u32 major;
> +	const u32 minor;
> +	const u32 rev;
>   	const struct amd_ip_funcs *funcs;
>   };
>   
> +struct amdgpu_ip_block {
> +	struct amdgpu_ip_block_status status;
> +	const struct amdgpu_ip_block_version *version;
> +};
> +
>   int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
>   				enum amd_ip_block_type type,
>   				u32 major, u32 minor);
>   
> -const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
> -					struct amdgpu_device *adev,
> -					enum amd_ip_block_type type);
> +struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
> +					     enum amd_ip_block_type type);
> +
> +int amdgpu_ip_block_add(struct amdgpu_device *adev,
> +			const struct amdgpu_ip_block_version *ip_block_version);
>   
>   /* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */
>   struct amdgpu_buffer_funcs {
> @@ -1271,14 +1288,6 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
>   typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
>   typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
>   
> -struct amdgpu_ip_block_status {
> -	bool valid;
> -	bool sw;
> -	bool hw;
> -	bool late_initialized;
> -	bool hang;
> -};
> -
>   struct amdgpu_device {
>   	struct device			*dev;
>   	struct drm_device		*ddev;
> @@ -1434,9 +1443,8 @@ struct amdgpu_device {
>   	/* GDS */
>   	struct amdgpu_gds		gds;
>   
> -	const struct amdgpu_ip_block_version *ip_blocks;
> +	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
>   	int				num_ip_blocks;
> -	struct amdgpu_ip_block_status	*ip_block_status;
>   	struct mutex	mn_lock;
>   	DECLARE_HASHTABLE(mn_hash, 7);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index 892d60f..2f9f96c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -265,14 +265,14 @@ static int acp_hw_init(void *handle)
>   
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> -	const struct amdgpu_ip_block_version *ip_version =
> +	const struct amdgpu_ip_block *ip_block =
>   		amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
>   
> -	if (!ip_version)
> +	if (!ip_block)
>   		return -EINVAL;
>   
>   	r = amd_acp_hw_init(adev->acp.cgs_device,
> -			    ip_version->major, ip_version->minor);
> +			    ip_block->version->major, ip_block->version->minor);
>   	/* -ENODEV means board uses AZ rather than ACP */
>   	if (r == -ENODEV)
>   		return 0;
> @@ -456,7 +456,7 @@ static int acp_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs acp_ip_funcs = {
> +static const struct amd_ip_funcs acp_ip_funcs = {
>   	.name = "acp_ip",
>   	.early_init = acp_early_init,
>   	.late_init = NULL,
> @@ -472,3 +472,12 @@ const struct amd_ip_funcs acp_ip_funcs = {
>   	.set_clockgating_state = acp_set_clockgating_state,
>   	.set_powergating_state = acp_set_powergating_state,
>   };
> +
> +const struct amdgpu_ip_block_version acp_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_ACP,
> +	.major = 2,
> +	.minor = 2,
> +	.rev = 0,
> +	.funcs = &acp_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
> index 8a39631..a288ce2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
> @@ -37,6 +37,6 @@ struct amdgpu_acp {
>   	struct acp_pm_domain *acp_genpd;
>   };
>   
> -extern const struct amd_ip_funcs acp_ip_funcs;
> +extern const struct amdgpu_ip_block_version acp_ip_block;
>   
>   #endif /* __AMDGPU_ACP_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index 34049d6..017556c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -626,11 +626,11 @@ static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
>   	int i, r = -1;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
>   
> -		if (adev->ip_blocks[i].type == block_type) {
> -			r = adev->ip_blocks[i].funcs->set_clockgating_state(
> +		if (adev->ip_blocks[i].version->type == block_type) {
> +			r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
>   								(void *)adev,
>   									state);
>   			break;
> @@ -647,11 +647,11 @@ static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
>   	int i, r = -1;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
>   
> -		if (adev->ip_blocks[i].type == block_type) {
> -			r = adev->ip_blocks[i].funcs->set_powergating_state(
> +		if (adev->ip_blocks[i].version->type == block_type) {
> +			r = adev->ip_blocks[i].version->funcs->set_powergating_state(
>   								(void *)adev,
>   									state);
>   			break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a67a572..5f51cda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1133,11 +1133,11 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
>   	int i, r = 0;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].type == block_type) {
> -			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
> -									    state);
> +		if (adev->ip_blocks[i].version->type == block_type) {
> +			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> +										     state);
>   			if (r)
>   				return r;
>   			break;
> @@ -1153,11 +1153,11 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
>   	int i, r = 0;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].type == block_type) {
> -			r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
> -									    state);
> +		if (adev->ip_blocks[i].version->type == block_type) {
> +			r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
> +										     state);
>   			if (r)
>   				return r;
>   			break;
> @@ -1172,10 +1172,10 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev,
>   	int i, r;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].type == block_type) {
> -			r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
> +		if (adev->ip_blocks[i].version->type == block_type) {
> +			r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
>   			if (r)
>   				return r;
>   			break;
> @@ -1191,23 +1191,22 @@ bool amdgpu_is_idle(struct amdgpu_device *adev,
>   	int i;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].type == block_type)
> -			return adev->ip_blocks[i].funcs->is_idle((void *)adev);
> +		if (adev->ip_blocks[i].version->type == block_type)
> +			return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
>   	}
>   	return true;
>   
>   }
>   
> -const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
> -					struct amdgpu_device *adev,
> -					enum amd_ip_block_type type)
> +struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
> +					     enum amd_ip_block_type type)
>   {
>   	int i;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++)
> -		if (adev->ip_blocks[i].type == type)
> +		if (adev->ip_blocks[i].version->type == type)
>   			return &adev->ip_blocks[i];
>   
>   	return NULL;
> @@ -1228,17 +1227,36 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
>   				enum amd_ip_block_type type,
>   				u32 major, u32 minor)
>   {
> -	const struct amdgpu_ip_block_version *ip_block;
> -	ip_block = amdgpu_get_ip_block(adev, type);
> +	struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
>   
> -	if (ip_block && ((ip_block->major > major) ||
> -			((ip_block->major == major) &&
> -			(ip_block->minor >= minor))))
> +	if (ip_block && ((ip_block->version->major > major) ||
> +			((ip_block->version->major == major) &&
> +			(ip_block->version->minor >= minor))))
>   		return 0;
>   
>   	return 1;
>   }
>   
> +/**
> + * amdgpu_ip_block_add
> + *
> + * @adev: amdgpu_device pointer
> + * @ip_block_version: pointer to the IP to add
> + *
> + * Adds the IP block driver information to the collection of IPs
> + * on the asic.
> + */
> +int amdgpu_ip_block_add(struct amdgpu_device *adev,
> +			const struct amdgpu_ip_block_version *ip_block_version)
> +{
> +	if (!ip_block_version)
> +		return -EINVAL;
> +
> +	adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
> +
> +	return 0;
> +}
> +
>   static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
>   {
>   	adev->enable_virtual_display = false;
> @@ -1339,33 +1357,24 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
>   		return -EINVAL;
>   	}
>   
> -	adev->ip_block_status = kcalloc(adev->num_ip_blocks,
> -					sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
> -	if (adev->ip_block_status == NULL)
> -		return -ENOMEM;
> -
> -	if (adev->ip_blocks == NULL) {
> -		DRM_ERROR("No IP blocks found!\n");
> -		return r;
> -	}
> -
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
>   		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
>   			DRM_ERROR("disabled ip block: %d\n", i);
> -			adev->ip_block_status[i].valid = false;
> +			adev->ip_blocks[i].status.valid = false;
>   		} else {
> -			if (adev->ip_blocks[i].funcs->early_init) {
> -				r = adev->ip_blocks[i].funcs->early_init((void *)adev);
> +			if (adev->ip_blocks[i].version->funcs->early_init) {
> +				r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
>   				if (r == -ENOENT) {
> -					adev->ip_block_status[i].valid = false;
> +					adev->ip_blocks[i].status.valid = false;
>   				} else if (r) {
> -					DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +					DRM_ERROR("early_init of IP block <%s> failed %d\n",
> +						  adev->ip_blocks[i].version->funcs->name, r);
>   					return r;
>   				} else {
> -					adev->ip_block_status[i].valid = true;
> +					adev->ip_blocks[i].status.valid = true;
>   				}
>   			} else {
> -				adev->ip_block_status[i].valid = true;
> +				adev->ip_blocks[i].status.valid = true;
>   			}
>   		}
>   	}
> @@ -1381,22 +1390,23 @@ static int amdgpu_init(struct amdgpu_device *adev)
>   	int i, r;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
> +		r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
>   		if (r) {
> -			DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_ERROR("sw_init of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   			return r;
>   		}
> -		adev->ip_block_status[i].sw = true;
> +		adev->ip_blocks[i].status.sw = true;
>   		/* need to do gmc hw init early so we can allocate gpu mem */
> -		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
> +		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
>   			r = amdgpu_vram_scratch_init(adev);
>   			if (r) {
>   				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
>   				return r;
>   			}
> -			r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
> +			r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
>   			if (r) {
>   				DRM_ERROR("hw_init %d failed %d\n", i, r);
>   				return r;
> @@ -1406,22 +1416,23 @@ static int amdgpu_init(struct amdgpu_device *adev)
>   				DRM_ERROR("amdgpu_wb_init failed %d\n", r);
>   				return r;
>   			}
> -			adev->ip_block_status[i].hw = true;
> +			adev->ip_blocks[i].status.hw = true;
>   		}
>   	}
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].sw)
> +		if (!adev->ip_blocks[i].status.sw)
>   			continue;
>   		/* gmc hw init is done early */
> -		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
> +		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
>   			continue;
> -		r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
> +		r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
>   		if (r) {
> -			DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_ERROR("hw_init of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   			return r;
>   		}
> -		adev->ip_block_status[i].hw = true;
> +		adev->ip_blocks[i].status.hw = true;
>   	}
>   
>   	return 0;
> @@ -1432,25 +1443,26 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
>   	int i = 0, r;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].funcs->late_init) {
> -			r = adev->ip_blocks[i].funcs->late_init((void *)adev);
> +		if (adev->ip_blocks[i].version->funcs->late_init) {
> +			r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
>   			if (r) {
> -				DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +				DRM_ERROR("late_init of IP block <%s> failed %d\n",
> +					  adev->ip_blocks[i].version->funcs->name, r);
>   				return r;
>   			}
> -			adev->ip_block_status[i].late_initialized = true;
> +			adev->ip_blocks[i].status.late_initialized = true;
>   		}
>   		/* skip CG for VCE/UVD, it's handled specially */
> -		if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
> -		    adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
> +		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
> +		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
>   			/* enable clockgating to save power */
> -			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
> -									    AMD_CG_STATE_GATE);
> +			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> +										     AMD_CG_STATE_GATE);
>   			if (r) {
>   				DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
> -					  adev->ip_blocks[i].funcs->name, r);
> +					  adev->ip_blocks[i].version->funcs->name, r);
>   				return r;
>   			}
>   		}
> @@ -1465,68 +1477,71 @@ static int amdgpu_fini(struct amdgpu_device *adev)
>   
>   	/* need to disable SMC first */
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].hw)
> +		if (!adev->ip_blocks[i].status.hw)
>   			continue;
> -		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
> +		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
>   			/* ungate blocks before hw fini so that we can shutdown the blocks safely */
> -			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
> -									    AMD_CG_STATE_UNGATE);
> +			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> +										     AMD_CG_STATE_UNGATE);
>   			if (r) {
>   				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
> -					  adev->ip_blocks[i].funcs->name, r);
> +					  adev->ip_blocks[i].version->funcs->name, r);
>   				return r;
>   			}
> -			r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
> +			r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
>   			/* XXX handle errors */
>   			if (r) {
>   				DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
> -					  adev->ip_blocks[i].funcs->name, r);
> +					  adev->ip_blocks[i].version->funcs->name, r);
>   			}
> -			adev->ip_block_status[i].hw = false;
> +			adev->ip_blocks[i].status.hw = false;
>   			break;
>   		}
>   	}
>   
>   	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> -		if (!adev->ip_block_status[i].hw)
> +		if (!adev->ip_blocks[i].status.hw)
>   			continue;
> -		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
> +		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
>   			amdgpu_wb_fini(adev);
>   			amdgpu_vram_scratch_fini(adev);
>   		}
>   		/* ungate blocks before hw fini so that we can shutdown the blocks safely */
> -		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
> -								    AMD_CG_STATE_UNGATE);
> +		r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> +									     AMD_CG_STATE_UNGATE);
>   		if (r) {
> -			DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   			return r;
>   		}
> -		r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
> +		r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
>   		/* XXX handle errors */
>   		if (r) {
> -			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   		}
> -		adev->ip_block_status[i].hw = false;
> +		adev->ip_blocks[i].status.hw = false;
>   	}
>   
>   	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> -		if (!adev->ip_block_status[i].sw)
> +		if (!adev->ip_blocks[i].status.sw)
>   			continue;
> -		r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
> +		r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
>   		/* XXX handle errors */
>   		if (r) {
> -			DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   		}
> -		adev->ip_block_status[i].sw = false;
> -		adev->ip_block_status[i].valid = false;
> +		adev->ip_blocks[i].status.sw = false;
> +		adev->ip_blocks[i].status.valid = false;
>   	}
>   
>   	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> -		if (!adev->ip_block_status[i].late_initialized)
> +		if (!adev->ip_blocks[i].status.late_initialized)
>   			continue;
> -		if (adev->ip_blocks[i].funcs->late_fini)
> -			adev->ip_blocks[i].funcs->late_fini((void *)adev);
> -		adev->ip_block_status[i].late_initialized = false;
> +		if (adev->ip_blocks[i].version->funcs->late_fini)
> +			adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
> +		adev->ip_blocks[i].status.late_initialized = false;
>   	}
>   
>   	return 0;
> @@ -1544,21 +1559,23 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
>   	}
>   
>   	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
>   		/* ungate blocks so that suspend can properly shut them down */
>   		if (i != AMD_IP_BLOCK_TYPE_SMC) {
> -			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
> -									    AMD_CG_STATE_UNGATE);
> +			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> +										     AMD_CG_STATE_UNGATE);
>   			if (r) {
> -				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
> +					  adev->ip_blocks[i].version->funcs->name, r);
>   			}
>   		}
>   		/* XXX handle errors */
> -		r = adev->ip_blocks[i].funcs->suspend(adev);
> +		r = adev->ip_blocks[i].version->funcs->suspend(adev);
>   		/* XXX handle errors */
>   		if (r) {
> -			DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_ERROR("suspend of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   		}
>   	}
>   
> @@ -1570,11 +1587,12 @@ static int amdgpu_resume(struct amdgpu_device *adev)
>   	int i, r;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		r = adev->ip_blocks[i].funcs->resume(adev);
> +		r = adev->ip_blocks[i].version->funcs->resume(adev);
>   		if (r) {
> -			DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
> +			DRM_ERROR("resume of IP block <%s> failed %d\n",
> +				  adev->ip_blocks[i].version->funcs->name, r);
>   			return r;
>   		}
>   	}
> @@ -1885,8 +1903,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
>   	drm_crtc_force_disable_all(adev->ddev);
>   	amdgpu_fbdev_fini(adev);
>   	r = amdgpu_fini(adev);
> -	kfree(adev->ip_block_status);
> -	adev->ip_block_status = NULL;
>   	adev->accel_working = false;
>   	/* free i2c buses */
>   	amdgpu_i2c_fini(adev);
> @@ -2125,13 +2141,13 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
>   	bool asic_hang = false;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].funcs->check_soft_reset)
> -			adev->ip_block_status[i].hang =
> -				adev->ip_blocks[i].funcs->check_soft_reset(adev);
> -		if (adev->ip_block_status[i].hang) {
> -			DRM_INFO("IP block:%d is hang!\n", i);
> +		if (adev->ip_blocks[i].version->funcs->check_soft_reset)
> +			adev->ip_blocks[i].status.hang =
> +				adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
> +		if (adev->ip_blocks[i].status.hang) {
> +			DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
>   			asic_hang = true;
>   		}
>   	}
> @@ -2143,11 +2159,11 @@ static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
>   	int i, r = 0;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_block_status[i].hang &&
> -		    adev->ip_blocks[i].funcs->pre_soft_reset) {
> -			r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
> +		if (adev->ip_blocks[i].status.hang &&
> +		    adev->ip_blocks[i].version->funcs->pre_soft_reset) {
> +			r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
>   			if (r)
>   				return r;
>   		}
> @@ -2161,13 +2177,13 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
>   	int i;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
> -		    (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
> -		    (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
> -		    (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
> -			if (adev->ip_block_status[i].hang) {
> +		if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
> +		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
> +		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
> +		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
> +			if (adev->ip_blocks[i].status.hang) {
>   				DRM_INFO("Some block need full reset!\n");
>   				return true;
>   			}
> @@ -2181,11 +2197,11 @@ static int amdgpu_soft_reset(struct amdgpu_device *adev)
>   	int i, r = 0;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_block_status[i].hang &&
> -		    adev->ip_blocks[i].funcs->soft_reset) {
> -			r = adev->ip_blocks[i].funcs->soft_reset(adev);
> +		if (adev->ip_blocks[i].status.hang &&
> +		    adev->ip_blocks[i].version->funcs->soft_reset) {
> +			r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
>   			if (r)
>   				return r;
>   		}
> @@ -2199,11 +2215,11 @@ static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
>   	int i, r = 0;
>   
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
> -		if (!adev->ip_block_status[i].valid)
> +		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_block_status[i].hang &&
> -		    adev->ip_blocks[i].funcs->post_soft_reset)
> -			r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
> +		if (adev->ip_blocks[i].status.hang &&
> +		    adev->ip_blocks[i].version->funcs->post_soft_reset)
> +			r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
>   		if (r)
>   			return r;
>   	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 3570124..d174246 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -306,10 +306,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
>   		}
>   
>   		for (i = 0; i < adev->num_ip_blocks; i++) {
> -			if (adev->ip_blocks[i].type == type &&
> -			    adev->ip_block_status[i].valid) {
> -				ip.hw_ip_version_major = adev->ip_blocks[i].major;
> -				ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
> +			if (adev->ip_blocks[i].version->type == type &&
> +			    adev->ip_blocks[i].status.valid) {
> +				ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
> +				ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
>   				ip.capabilities_flags = 0;
>   				ip.available_rings = ring_mask;
>   				ip.ib_start_alignment = ib_start_alignment;
> @@ -345,8 +345,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
>   		}
>   
>   		for (i = 0; i < adev->num_ip_blocks; i++)
> -			if (adev->ip_blocks[i].type == type &&
> -			    adev->ip_block_status[i].valid &&
> +			if (adev->ip_blocks[i].version->type == type &&
> +			    adev->ip_blocks[i].status.valid &&
>   			    count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
>   				count++;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index 7532ff8..fa6baf3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -299,7 +299,7 @@ static int amdgpu_pp_soft_reset(void *handle)
>   	return ret;
>   }
>   
> -const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
> +static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
>   	.name = "amdgpu_powerplay",
>   	.early_init = amdgpu_pp_early_init,
>   	.late_init = amdgpu_pp_late_init,
> @@ -316,3 +316,12 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
>   	.set_clockgating_state = amdgpu_pp_set_clockgating_state,
>   	.set_powergating_state = amdgpu_pp_set_powergating_state,
>   };
> +
> +const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SMC,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &amdgpu_pp_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
> index ee6ea6c..c0c4bfd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
> @@ -28,6 +28,6 @@
>   
>   #include "amd_shared.h"
>   
> -extern const struct amd_ip_funcs amdgpu_pp_ip_funcs;
> +extern const struct amdgpu_ip_block_version amdgpu_pp_ip_block;
>   
>   #endif /* __AMDGPU_POWERPLAY_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index da66823..ded57dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -346,7 +346,7 @@ error:
>   static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> -	const struct amdgpu_ip_block_version *ip_block;
> +	const struct amdgpu_ip_block *ip_block;
>   
>   	if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
>   		/* only compute rings */
> @@ -356,10 +356,10 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
>   	if (!ip_block)
>   		return false;
>   
> -	if (ip_block->major <= 7) {
> +	if (ip_block->version->major <= 7) {
>   		/* gfx7 has no workaround */
>   		return true;
> -	} else if (ip_block->major == 8) {
> +	} else if (ip_block->version->major == 8) {
>   		if (adev->gfx.mec_fw_version >= 673)
>   			/* gfx8 is fixed in MEC firmware 673 */
>   			return false;
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index 3f89107..885f08c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -6663,3 +6663,12 @@ static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
>   	adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version ci_dpm_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SMC,
> +	.major = 7,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &ci_dpm_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index a845b6a..1b70f8fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -1641,745 +1641,6 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
>   		adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
>   }
>   
> -static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &dce_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 5,
> -		.rev = 0,
> -		.funcs = &dce_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 5,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &dce_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &dce_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &dce_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 8,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &gfx_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cik_sdma_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 4,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &uvd_v4_2_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v2_0_ip_funcs,
> -	},
> -};
> -
> -int cik_set_ip_blocks(struct amdgpu_device *adev)
> -{
> -	if (adev->enable_virtual_display) {
> -		switch (adev->asic_type) {
> -		case CHIP_BONAIRE:
> -			adev->ip_blocks = bonaire_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
> -			break;
> -		case CHIP_HAWAII:
> -			adev->ip_blocks = hawaii_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
> -			break;
> -		case CHIP_KAVERI:
> -			adev->ip_blocks = kaveri_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
> -			break;
> -		case CHIP_KABINI:
> -			adev->ip_blocks = kabini_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
> -			break;
> -		case CHIP_MULLINS:
> -			adev->ip_blocks = mullins_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
> -			break;
> -		default:
> -			/* FIXME: not supported yet */
> -			return -EINVAL;
> -		}
> -	} else {
> -		switch (adev->asic_type) {
> -		case CHIP_BONAIRE:
> -			adev->ip_blocks = bonaire_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
> -			break;
> -		case CHIP_HAWAII:
> -			adev->ip_blocks = hawaii_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
> -			break;
> -		case CHIP_KAVERI:
> -			adev->ip_blocks = kaveri_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
> -			break;
> -		case CHIP_KABINI:
> -			adev->ip_blocks = kabini_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
> -			break;
> -		case CHIP_MULLINS:
> -			adev->ip_blocks = mullins_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
> -			break;
> -		default:
> -			/* FIXME: not supported yet */
> -			return -EINVAL;
> -		}
> -	}
> -
> -	return 0;
> -}
> -
>   static const struct amdgpu_asic_funcs cik_asic_funcs =
>   {
>   	.read_disabled_bios = &cik_read_disabled_bios,
> @@ -2612,7 +1873,7 @@ static int cik_common_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs cik_common_ip_funcs = {
> +static const struct amd_ip_funcs cik_common_ip_funcs = {
>   	.name = "cik_common",
>   	.early_init = cik_common_early_init,
>   	.late_init = NULL,
> @@ -2628,3 +1889,79 @@ const struct amd_ip_funcs cik_common_ip_funcs = {
>   	.set_clockgating_state = cik_common_set_clockgating_state,
>   	.set_powergating_state = cik_common_set_powergating_state,
>   };
> +
> +static const struct amdgpu_ip_block_version cik_common_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_COMMON,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &cik_common_ip_funcs,
> +};
> +
> +int cik_set_ip_blocks(struct amdgpu_device *adev)
> +{
> +	switch (adev->asic_type) {
> +	case CHIP_BONAIRE:
> +		amdgpu_ip_block_add(adev, &cik_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
> +		break;
> +	case CHIP_HAWAII:
> +		amdgpu_ip_block_add(adev, &cik_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
> +		break;
> +	case CHIP_KAVERI:
> +		amdgpu_ip_block_add(adev, &cik_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
> +		break;
> +	case CHIP_KABINI:
> +	case CHIP_MULLINS:
> +		amdgpu_ip_block_add(adev, &cik_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
> +		amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
> +		break;
> +	default:
> +		/* FIXME: not supported yet */
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
> index 5ebd2d7..c4989f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.h
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.h
> @@ -24,8 +24,6 @@
>   #ifndef __CIK_H__
>   #define __CIK_H__
>   
> -extern const struct amd_ip_funcs cik_common_ip_funcs;
> -
>   void cik_srbm_select(struct amdgpu_device *adev,
>   		     u32 me, u32 pipe, u32 queue, u32 vmid);
>   int cik_set_ip_blocks(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index be3d6f7..319b32c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -413,7 +413,7 @@ static int cik_ih_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs cik_ih_ip_funcs = {
> +static const struct amd_ip_funcs cik_ih_ip_funcs = {
>   	.name = "cik_ih",
>   	.early_init = cik_ih_early_init,
>   	.late_init = NULL,
> @@ -441,3 +441,12 @@ static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>   	if (adev->irq.ih_funcs == NULL)
>   		adev->irq.ih_funcs = &cik_ih_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version cik_ih_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_IH,
> +	.major = 2,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &cik_ih_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
> index 6b0f375..1d9ddee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
> @@ -24,6 +24,6 @@
>   #ifndef __CIK_IH_H__
>   #define __CIK_IH_H__
>   
> -extern const struct amd_ip_funcs cik_ih_ip_funcs;
> +extern const struct amdgpu_ip_block_version cik_ih_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index b96ef20..c7340b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1190,7 +1190,7 @@ static int cik_sdma_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs cik_sdma_ip_funcs = {
> +static const struct amd_ip_funcs cik_sdma_ip_funcs = {
>   	.name = "cik_sdma",
>   	.early_init = cik_sdma_early_init,
>   	.late_init = NULL,
> @@ -1342,3 +1342,12 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
>   		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
>   	}
>   }
> +
> +const struct amdgpu_ip_block_version cik_sdma_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SDMA,
> +	.major = 2,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &cik_sdma_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
> index 027727c..a4a8fe0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
> @@ -24,6 +24,6 @@
>   #ifndef __CIK_SDMA_H__
>   #define __CIK_SDMA_H__
>   
> -extern const struct amd_ip_funcs cik_sdma_ip_funcs;
> +extern const struct amdgpu_ip_block_version cik_sdma_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
> index 3c082e14..ad2cc4b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
> @@ -2296,3 +2296,12 @@ static void cz_dpm_set_funcs(struct amdgpu_device *adev)
>   	if (NULL == adev->pm.funcs)
>   		adev->pm.funcs = &cz_dpm_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version cz_dpm_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SMC,
> +	.major = 8,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &cz_dpm_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 3d23a70..fe7cbb2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -394,7 +394,7 @@ static int cz_ih_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs cz_ih_ip_funcs = {
> +static const struct amd_ip_funcs cz_ih_ip_funcs = {
>   	.name = "cz_ih",
>   	.early_init = cz_ih_early_init,
>   	.late_init = NULL,
> @@ -423,3 +423,11 @@ static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>   		adev->irq.ih_funcs = &cz_ih_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version cz_ih_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_IH,
> +	.major = 3,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &cz_ih_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
> index fc4057a..14be775 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
> @@ -24,6 +24,6 @@
>   #ifndef __CZ_IH_H__
>   #define __CZ_IH_H__
>   
> -extern const struct amd_ip_funcs cz_ih_ip_funcs;
> +extern const struct amdgpu_ip_block_version cz_ih_ip_block;
>   
>   #endif /* __CZ_IH_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 15c3833..e5d0edf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3470,7 +3470,7 @@ static int dce_v10_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs dce_v10_0_ip_funcs = {
> +static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
>   	.name = "dce_v10_0",
>   	.early_init = dce_v10_0_early_init,
>   	.late_init = NULL,
> @@ -3801,3 +3801,21 @@ static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
>   	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version dce_v10_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 10,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &dce_v10_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v10_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 10,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &dce_v10_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
> index e3dc04d..7a07477 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
> @@ -24,7 +24,9 @@
>   #ifndef __DCE_V10_0_H__
>   #define __DCE_V10_0_H__
>   
> -extern const struct amd_ip_funcs dce_v10_0_ip_funcs;
> +
> +extern const struct amdgpu_ip_block_version dce_v10_0_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v10_1_ip_block;
>   
>   void dce_v10_0_disable_dce(struct amdgpu_device *adev);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 2696428..9719b2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3527,7 +3527,7 @@ static int dce_v11_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs dce_v11_0_ip_funcs = {
> +static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
>   	.name = "dce_v11_0",
>   	.early_init = dce_v11_0_early_init,
>   	.late_init = NULL,
> @@ -3857,3 +3857,21 @@ static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
>   	adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version dce_v11_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 11,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &dce_v11_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v11_2_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 11,
> +	.minor = 2,
> +	.rev = 0,
> +	.funcs = &dce_v11_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
> index 1f58a65..0d878ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
> @@ -24,7 +24,8 @@
>   #ifndef __DCE_V11_0_H__
>   #define __DCE_V11_0_H__
>   
> -extern const struct amd_ip_funcs dce_v11_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version dce_v11_0_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v11_2_ip_block;
>   
>   void dce_v11_0_disable_dce(struct amdgpu_device *adev);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 502e979..44547f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2734,7 +2734,7 @@ static int dce_v6_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs dce_v6_0_ip_funcs = {
> +static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
>   	.name = "dce_v6_0",
>   	.early_init = dce_v6_0_early_init,
>   	.late_init = NULL,
> @@ -3075,3 +3075,21 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
>   	adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version dce_v6_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 6,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &dce_v6_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v6_4_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 6,
> +	.minor = 4,
> +	.rev = 0,
> +	.funcs = &dce_v6_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> index 4c6cd18..7b546b5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
> @@ -24,7 +24,8 @@
>   #ifndef __DCE_V6_0_H__
>   #define __DCE_V6_0_H__
>   
> -extern const struct amd_ip_funcs dce_v6_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version dce_v6_0_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v6_4_ip_block;
>   
>   void dce_v6_0_disable_dce(struct amdgpu_device *adev);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 0245ed6..16a2f1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3308,7 +3308,7 @@ static int dce_v8_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs dce_v8_0_ip_funcs = {
> +static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
>   	.name = "dce_v8_0",
>   	.early_init = dce_v8_0_early_init,
>   	.late_init = NULL,
> @@ -3638,3 +3638,48 @@ static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
>   	adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version dce_v8_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 8,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &dce_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v8_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 8,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &dce_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v8_2_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 8,
> +	.minor = 2,
> +	.rev = 0,
> +	.funcs = &dce_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v8_3_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 8,
> +	.minor = 3,
> +	.rev = 0,
> +	.funcs = &dce_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version dce_v8_5_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 8,
> +	.minor = 5,
> +	.rev = 0,
> +	.funcs = &dce_v8_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
> index 7d0770c..13b802d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
> @@ -24,7 +24,11 @@
>   #ifndef __DCE_V8_0_H__
>   #define __DCE_V8_0_H__
>   
> -extern const struct amd_ip_funcs dce_v8_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version dce_v8_0_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v8_1_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v8_2_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v8_3_ip_block;
> +extern const struct amdgpu_ip_block_version dce_v8_5_ip_block;
>   
>   void dce_v8_0_disable_dce(struct amdgpu_device *adev);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 632a385..b5ae41d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -574,7 +574,7 @@ static int dce_virtual_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs dce_virtual_ip_funcs = {
> +static const struct amd_ip_funcs dce_virtual_ip_funcs = {
>   	.name = "dce_virtual",
>   	.early_init = dce_virtual_early_init,
>   	.late_init = NULL,
> @@ -824,3 +824,11 @@ static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version dce_virtual_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_DCE,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &dce_virtual_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.h b/drivers/gpu/drm/amd/amdgpu/dce_virtual.h
> index 393ce97..ed42201 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.h
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.h
> @@ -24,7 +24,7 @@
>   #ifndef __DCE_VIRTUAL_H__
>   #define __DCE_VIRTUAL_H__
>   
> -extern const struct amd_ip_funcs dce_virtual_ip_funcs;
> +extern const struct amdgpu_ip_block_version dce_virtual_ip_block;
>   
>   #endif
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 367b14e..96dd05d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3206,7 +3206,7 @@ static int gfx_v6_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
> +static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
>   	.name = "gfx_v6_0",
>   	.early_init = gfx_v6_0_early_init,
>   	.late_init = NULL,
> @@ -3344,3 +3344,12 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
>   	cu_info->number = active_cu_number;
>   	cu_info->ao_cu_mask = ao_cu_mask;
>   }
> +
> +const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 6,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &gfx_v6_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
> index b9657e7..ced6fc4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
> @@ -24,6 +24,6 @@
>   #ifndef __GFX_V6_0_H__
>   #define __GFX_V6_0_H__
>   
> -extern const struct amd_ip_funcs gfx_v6_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version gfx_v6_0_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 3886497..bc6ccd0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -5087,7 +5087,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
> +static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
>   	.name = "gfx_v7_0",
>   	.early_init = gfx_v7_0_early_init,
>   	.late_init = gfx_v7_0_late_init,
> @@ -5270,3 +5270,39 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
>   	cu_info->number = active_cu_number;
>   	cu_info->ao_cu_mask = ao_cu_mask;
>   }
> +
> +const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 7,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &gfx_v7_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 7,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &gfx_v7_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 7,
> +	.minor = 2,
> +	.rev = 0,
> +	.funcs = &gfx_v7_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 7,
> +	.minor = 3,
> +	.rev = 0,
> +	.funcs = &gfx_v7_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> index 94e3ea1..2f5164c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> @@ -24,6 +24,9 @@
>   #ifndef __GFX_V7_0_H__
>   #define __GFX_V7_0_H__
>   
> -extern const struct amd_ip_funcs gfx_v7_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version gfx_v7_0_ip_block;
> +extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block;
> +extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block;
> +extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 6f3996f..27b3de4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6504,7 +6504,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
> +static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
>   	.name = "gfx_v8_0",
>   	.early_init = gfx_v8_0_early_init,
>   	.late_init = gfx_v8_0_late_init,
> @@ -6734,3 +6734,21 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
>   	cu_info->number = active_cu_number;
>   	cu_info->ao_cu_mask = ao_cu_mask;
>   }
> +
> +const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 8,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &gfx_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GFX,
> +	.major = 8,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &gfx_v8_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
> index ebed1f8..788cc3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
> @@ -24,6 +24,7 @@
>   #ifndef __GFX_V8_0_H__
>   #define __GFX_V8_0_H__
>   
> -extern const struct amd_ip_funcs gfx_v8_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version gfx_v8_0_ip_block;
> +extern const struct amdgpu_ip_block_version gfx_v8_1_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index b13c8aa..1940d36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -1030,7 +1030,7 @@ static int gmc_v6_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
> +static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
>   	.name = "gmc_v6_0",
>   	.early_init = gmc_v6_0_early_init,
>   	.late_init = gmc_v6_0_late_init,
> @@ -1069,3 +1069,11 @@ static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GMC,
> +	.major = 6,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &gmc_v6_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
> index 42c4fc6..ed2f64d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
> @@ -24,6 +24,6 @@
>   #ifndef __GMC_V6_0_H__
>   #define __GMC_V6_0_H__
>   
> -extern const struct amd_ip_funcs gmc_v6_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version gmc_v6_0_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index aa0c4b9..3a25f72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1235,7 +1235,7 @@ static int gmc_v7_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
> +static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
>   	.name = "gmc_v7_0",
>   	.early_init = gmc_v7_0_early_init,
>   	.late_init = gmc_v7_0_late_init,
> @@ -1273,3 +1273,21 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->mc.vm_fault.num_types = 1;
>   	adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GMC,
> +	.major = 7,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &gmc_v7_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GMC,
> +	.major = 7,
> +	.minor = 4,
> +	.rev = 0,
> +	.funcs = &gmc_v7_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
> index 0b386b5..ebce296 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
> @@ -24,6 +24,7 @@
>   #ifndef __GMC_V7_0_H__
>   #define __GMC_V7_0_H__
>   
> -extern const struct amd_ip_funcs gmc_v7_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version gmc_v7_0_ip_block;
> +extern const struct amdgpu_ip_block_version gmc_v7_4_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index c22ef14..74d7cc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1436,7 +1436,7 @@ static int gmc_v8_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
> +static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
>   	.name = "gmc_v8_0",
>   	.early_init = gmc_v8_0_early_init,
>   	.late_init = gmc_v8_0_late_init,
> @@ -1477,3 +1477,30 @@ static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->mc.vm_fault.num_types = 1;
>   	adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GMC,
> +	.major = 8,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &gmc_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GMC,
> +	.major = 8,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &gmc_v8_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_GMC,
> +	.major = 8,
> +	.minor = 5,
> +	.rev = 0,
> +	.funcs = &gmc_v8_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
> index fc5001a..19b8a8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
> @@ -24,6 +24,8 @@
>   #ifndef __GMC_V8_0_H__
>   #define __GMC_V8_0_H__
>   
> -extern const struct amd_ip_funcs gmc_v8_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version gmc_v8_0_ip_block;
> +extern const struct amdgpu_ip_block_version gmc_v8_1_ip_block;
> +extern const struct amdgpu_ip_block_version gmc_v8_5_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 3b8906c..ac21bb7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -392,7 +392,7 @@ static int iceland_ih_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs iceland_ih_ip_funcs = {
> +static const struct amd_ip_funcs iceland_ih_ip_funcs = {
>   	.name = "iceland_ih",
>   	.early_init = iceland_ih_early_init,
>   	.late_init = NULL,
> @@ -421,3 +421,11 @@ static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>   		adev->irq.ih_funcs = &iceland_ih_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version iceland_ih_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_IH,
> +	.major = 2,
> +	.minor = 4,
> +	.rev = 0,
> +	.funcs = &iceland_ih_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
> index 57558cd..3235f42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
> @@ -24,6 +24,6 @@
>   #ifndef __ICELAND_IH_H__
>   #define __ICELAND_IH_H__
>   
> -extern const struct amd_ip_funcs iceland_ih_ip_funcs;
> +extern const struct amdgpu_ip_block_version iceland_ih_ip_block;
>   
>   #endif /* __ICELAND_IH_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> index c3367d6..42e5c94 100644
> --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> @@ -3292,3 +3292,12 @@ static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
>   	adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version kv_dpm_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SMC,
> +	.major = 7,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &kv_dpm_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 5859a10..03e8856 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1187,7 +1187,7 @@ static int sdma_v2_4_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
> +static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
>   	.name = "sdma_v2_4",
>   	.early_init = sdma_v2_4_early_init,
>   	.late_init = NULL,
> @@ -1340,3 +1340,12 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
>   		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
>   	}
>   }
> +
> +const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SDMA,
> +	.major = 2,
> +	.minor = 4,
> +	.rev = 0,
> +	.funcs = &sdma_v2_4_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
> index 07349f5..28b4337 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
> @@ -24,6 +24,6 @@
>   #ifndef __SDMA_V2_4_H__
>   #define __SDMA_V2_4_H__
>   
> -extern const struct amd_ip_funcs sdma_v2_4_ip_funcs;
> +extern const struct amdgpu_ip_block_version sdma_v2_4_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 24642f9..6172d01 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1527,7 +1527,7 @@ static int sdma_v3_0_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
> +static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
>   	.name = "sdma_v3_0",
>   	.early_init = sdma_v3_0_early_init,
>   	.late_init = NULL,
> @@ -1683,3 +1683,21 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
>   		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
>   	}
>   }
> +
> +const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SDMA,
> +	.major = 3,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &sdma_v3_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SDMA,
> +	.major = 3,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &sdma_v3_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
> index 0cb9698..7aa223d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
> @@ -24,6 +24,7 @@
>   #ifndef __SDMA_V3_0_H__
>   #define __SDMA_V3_0_H__
>   
> -extern const struct amd_ip_funcs sdma_v3_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version sdma_v3_0_ip_block;
> +extern const struct amdgpu_ip_block_version sdma_v3_1_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 1d40c26..d2d7920 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -1812,7 +1812,7 @@ static int si_common_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs si_common_ip_funcs = {
> +static const struct amd_ip_funcs si_common_ip_funcs = {
>   	.name = "si_common",
>   	.early_init = si_common_early_init,
>   	.late_init = NULL,
> @@ -1829,240 +1829,13 @@ const struct amd_ip_funcs si_common_ip_funcs = {
>   	.set_powergating_state = si_common_set_powergating_state,
>   };
>   
> -static const struct amdgpu_ip_block_version verde_ip_blocks[] =
> +static const struct amdgpu_ip_block_version si_common_ip_block =
>   {
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_dma_ip_funcs,
> -	},
> -/*	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 3,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &si_null_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_null_ip_funcs,
> -	},
> -	*/
> -};
> -
> -
> -static const struct amdgpu_ip_block_version verde_ip_blocks_vd[] =
> -{
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_dma_ip_funcs,
> -	},
> -/*	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 3,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &si_null_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_null_ip_funcs,
> -	},
> -	*/
> -};
> -
> -static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
> -{
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_dma_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version hainan_ip_blocks_vd[] =
> -{
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &si_dma_ip_funcs,
> -	},
> +	.type = AMD_IP_BLOCK_TYPE_COMMON,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &si_common_ip_funcs,
>   };
>   
>   int si_set_ip_blocks(struct amdgpu_device *adev)
> @@ -2071,23 +1844,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
>   	case CHIP_VERDE:
>   	case CHIP_TAHITI:
>   	case CHIP_PITCAIRN:
> +		amdgpu_ip_block_add(adev, &si_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &si_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &si_dma_ip_block);
> +		/* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
> +		/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
> +		break;
>   	case CHIP_OLAND:
> -		if (adev->enable_virtual_display) {
> -			adev->ip_blocks = verde_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks_vd);
> -		} else {
> -			adev->ip_blocks = verde_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks);
> -		}
> +		amdgpu_ip_block_add(adev, &si_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &si_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &si_dma_ip_block);
> +		/* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
> +		/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
>   		break;
>   	case CHIP_HAINAN:
> -		if (adev->enable_virtual_display) {
> -			adev->ip_blocks = hainan_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks_vd);
> -		} else {
> -			adev->ip_blocks = hainan_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks);
> -		}
> +		amdgpu_ip_block_add(adev, &si_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &si_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &si_dma_ip_block);
>   		break;
>   	default:
>   		BUG();
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.h b/drivers/gpu/drm/amd/amdgpu/si.h
> index 959d7b6..5892250 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.h
> +++ b/drivers/gpu/drm/amd/amdgpu/si.h
> @@ -24,8 +24,6 @@
>   #ifndef __SI_H__
>   #define __SI_H__
>   
> -extern const struct amd_ip_funcs si_common_ip_funcs;
> -
>   void si_srbm_select(struct amdgpu_device *adev,
>   		     u32 me, u32 pipe, u32 queue, u32 vmid);
>   int si_set_ip_blocks(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 7fece1f..14265c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -745,7 +745,7 @@ static int si_dma_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs si_dma_ip_funcs = {
> +static const struct amd_ip_funcs si_dma_ip_funcs = {
>   	.name = "si_dma",
>   	.early_init = si_dma_early_init,
>   	.late_init = NULL,
> @@ -903,3 +903,12 @@ static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
>   		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
>   	}
>   }
> +
> +const struct amdgpu_ip_block_version si_dma_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SDMA,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &si_dma_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.h b/drivers/gpu/drm/amd/amdgpu/si_dma.h
> index 3a3e0c7..5ac1b84 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.h
> @@ -24,6 +24,6 @@
>   #ifndef __SI_DMA_H__
>   #define __SI_DMA_H__
>   
> -extern const struct amd_ip_funcs si_dma_ip_funcs;
> +extern const struct amdgpu_ip_block_version si_dma_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index 38b4b97..6e6c7ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -8011,3 +8011,11 @@ static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version si_dpm_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_SMC,
> +	.major = 6,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &si_dpm_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 8fae3d4..db0f368 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -268,7 +268,7 @@ static int si_ih_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs si_ih_ip_funcs = {
> +static const struct amd_ip_funcs si_ih_ip_funcs = {
>   	.name = "si_ih",
>   	.early_init = si_ih_early_init,
>   	.late_init = NULL,
> @@ -297,3 +297,11 @@ static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>   		adev->irq.ih_funcs = &si_ih_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version si_ih_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_IH,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &si_ih_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.h b/drivers/gpu/drm/amd/amdgpu/si_ih.h
> index f3e3a95..42e64a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.h
> @@ -24,6 +24,6 @@
>   #ifndef __SI_IH_H__
>   #define __SI_IH_H__
>   
> -extern const struct amd_ip_funcs si_ih_ip_funcs;
> +extern const struct amdgpu_ip_block_version si_ih_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index b4ea229..52b71ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -455,7 +455,7 @@ static int tonga_ih_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs tonga_ih_ip_funcs = {
> +static const struct amd_ip_funcs tonga_ih_ip_funcs = {
>   	.name = "tonga_ih",
>   	.early_init = tonga_ih_early_init,
>   	.late_init = NULL,
> @@ -487,3 +487,11 @@ static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>   		adev->irq.ih_funcs = &tonga_ih_funcs;
>   }
>   
> +const struct amdgpu_ip_block_version tonga_ih_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_IH,
> +	.major = 3,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &tonga_ih_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
> index 7392d70..499027e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
> @@ -24,6 +24,6 @@
>   #ifndef __TONGA_IH_H__
>   #define __TONGA_IH_H__
>   
> -extern const struct amd_ip_funcs tonga_ih_ip_funcs;
> +extern const struct amdgpu_ip_block_version tonga_ih_ip_block;
>   
> -#endif /* __CZ_IH_H__ */
> +#endif /* __TONGA_IH_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 1bab75a..3c2dce6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -723,7 +723,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
>   	}
>   }
>   
> -const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
> +static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
>   	.name = "uvd_v4_2",
>   	.early_init = uvd_v4_2_early_init,
>   	.late_init = NULL,
> @@ -780,3 +780,12 @@ static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->uvd.irq.num_types = 1;
>   	adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version uvd_v4_2_ip_block =
> +{
> +		.type = AMD_IP_BLOCK_TYPE_UVD,
> +		.major = 4,
> +		.minor = 2,
> +		.rev = 0,
> +		.funcs = &uvd_v4_2_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
> index 0a615dd..8a0444b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
> @@ -24,6 +24,6 @@
>   #ifndef __UVD_V4_2_H__
>   #define __UVD_V4_2_H__
>   
> -extern const struct amd_ip_funcs uvd_v4_2_ip_funcs;
> +extern const struct amdgpu_ip_block_version uvd_v4_2_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index ec848fc..05088ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -774,7 +774,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
>   	}
>   }
>   
> -const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> +static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
>   	.name = "uvd_v5_0",
>   	.early_init = uvd_v5_0_early_init,
>   	.late_init = NULL,
> @@ -831,3 +831,12 @@ static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->uvd.irq.num_types = 1;
>   	adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
> +{
> +		.type = AMD_IP_BLOCK_TYPE_UVD,
> +		.major = 5,
> +		.minor = 0,
> +		.rev = 0,
> +		.funcs = &uvd_v5_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
> index e3b3c49..2eaaea7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
> @@ -24,6 +24,6 @@
>   #ifndef __UVD_V5_0_H__
>   #define __UVD_V5_0_H__
>   
> -extern const struct amd_ip_funcs uvd_v5_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version uvd_v5_0_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index be91293..2e2baa6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1001,7 +1001,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
>   	}
>   }
>   
> -const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> +static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
>   	.name = "uvd_v6_0",
>   	.early_init = uvd_v6_0_early_init,
>   	.late_init = NULL,
> @@ -1096,3 +1096,30 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->uvd.irq.num_types = 1;
>   	adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
>   }
> +
> +const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
> +{
> +		.type = AMD_IP_BLOCK_TYPE_UVD,
> +		.major = 6,
> +		.minor = 0,
> +		.rev = 0,
> +		.funcs = &uvd_v6_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
> +{
> +		.type = AMD_IP_BLOCK_TYPE_UVD,
> +		.major = 6,
> +		.minor = 2,
> +		.rev = 0,
> +		.funcs = &uvd_v6_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
> +{
> +		.type = AMD_IP_BLOCK_TYPE_UVD,
> +		.major = 6,
> +		.minor = 3,
> +		.rev = 0,
> +		.funcs = &uvd_v6_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
> index 6b92a23..d3d48c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
> @@ -24,6 +24,8 @@
>   #ifndef __UVD_V6_0_H__
>   #define __UVD_V6_0_H__
>   
> -extern const struct amd_ip_funcs uvd_v6_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version uvd_v6_0_ip_block;
> +extern const struct amdgpu_ip_block_version uvd_v6_2_ip_block;
> +extern const struct amdgpu_ip_block_version uvd_v6_3_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index d585839..38ed903 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -592,7 +592,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
>   		return vce_v2_0_start(adev);
>   }
>   
> -const struct amd_ip_funcs vce_v2_0_ip_funcs = {
> +static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
>   	.name = "vce_v2_0",
>   	.early_init = vce_v2_0_early_init,
>   	.late_init = NULL,
> @@ -647,3 +647,12 @@ static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->vce.irq.num_types = 1;
>   	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
>   };
> +
> +const struct amdgpu_ip_block_version vce_v2_0_ip_block =
> +{
> +		.type = AMD_IP_BLOCK_TYPE_VCE,
> +		.major = 2,
> +		.minor = 0,
> +		.rev = 0,
> +		.funcs = &vce_v2_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
> index 0d2ae8a..4d15167 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
> @@ -24,6 +24,6 @@
>   #ifndef __VCE_V2_0_H__
>   #define __VCE_V2_0_H__
>   
> -extern const struct amd_ip_funcs vce_v2_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version vce_v2_0_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 589fff1..3f899e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -807,7 +807,7 @@ static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
>   	amdgpu_ring_write(ring, seq);
>   }
>   
> -const struct amd_ip_funcs vce_v3_0_ip_funcs = {
> +static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
>   	.name = "vce_v3_0",
>   	.early_init = vce_v3_0_early_init,
>   	.late_init = NULL,
> @@ -898,3 +898,30 @@ static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
>   	adev->vce.irq.num_types = 1;
>   	adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
>   };
> +
> +const struct amdgpu_ip_block_version vce_v3_0_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_VCE,
> +	.major = 3,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &vce_v3_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version vce_v3_1_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_VCE,
> +	.major = 3,
> +	.minor = 1,
> +	.rev = 0,
> +	.funcs = &vce_v3_0_ip_funcs,
> +};
> +
> +const struct amdgpu_ip_block_version vce_v3_4_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_VCE,
> +	.major = 3,
> +	.minor = 4,
> +	.rev = 0,
> +	.funcs = &vce_v3_0_ip_funcs,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
> index b45af65..08b908c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
> @@ -24,6 +24,8 @@
>   #ifndef __VCE_V3_0_H__
>   #define __VCE_V3_0_H__
>   
> -extern const struct amd_ip_funcs vce_v3_0_ip_funcs;
> +extern const struct amdgpu_ip_block_version vce_v3_0_ip_block;
> +extern const struct amdgpu_ip_block_version vce_v3_1_ip_block;
> +extern const struct amdgpu_ip_block_version vce_v3_4_ip_block;
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 82f72cd..e33399c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -858,734 +858,6 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
>   	WREG32(mmBIF_DOORBELL_APER_EN, tmp);
>   }
>   
> -/* topaz has no DCE, UVD, VCE */
> -static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &iceland_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &sdma_v2_4_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version topaz_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 7,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &gmc_v7_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 2,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &iceland_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 1,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 2,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &sdma_v2_4_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &tonga_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 10,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_v10_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 5,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &uvd_v5_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &tonga_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 10,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 5,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &uvd_v5_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 5,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &tonga_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 10,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &dce_v10_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &uvd_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 5,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &tonga_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 10,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &uvd_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &tonga_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 11,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &dce_v11_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 6,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &uvd_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &tonga_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 7,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 11,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 1,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 6,
> -		.minor = 3,
> -		.rev = 0,
> -		.funcs = &uvd_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 4,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -};
> -
> -static const struct amdgpu_ip_block_version cz_ip_blocks[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cz_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 11,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_v11_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &uvd_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -#if defined(CONFIG_DRM_AMD_ACP)
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_ACP,
> -		.major = 2,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &acp_ip_funcs,
> -	},
> -#endif
> -};
> -
> -static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
> -{
> -	/* ORDER MATTERS! */
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_COMMON,
> -		.major = 2,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vi_common_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GMC,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gmc_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_IH,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &cz_ih_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SMC,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &amdgpu_pp_ip_funcs
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_DCE,
> -		.major = 11,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &dce_virtual_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_GFX,
> -		.major = 8,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &gfx_v8_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_SDMA,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &sdma_v3_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_UVD,
> -		.major = 6,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &uvd_v6_0_ip_funcs,
> -	},
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_VCE,
> -		.major = 3,
> -		.minor = 0,
> -		.rev = 0,
> -		.funcs = &vce_v3_0_ip_funcs,
> -	},
> -#if defined(CONFIG_DRM_AMD_ACP)
> -	{
> -		.type = AMD_IP_BLOCK_TYPE_ACP,
> -		.major = 2,
> -		.minor = 2,
> -		.rev = 0,
> -		.funcs = &acp_ip_funcs,
> -	},
> -#endif
> -};
> -
> -int vi_set_ip_blocks(struct amdgpu_device *adev)
> -{
> -	if (adev->enable_virtual_display) {
> -		switch (adev->asic_type) {
> -		case CHIP_TOPAZ:
> -			adev->ip_blocks = topaz_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks_vd);
> -			break;
> -		case CHIP_FIJI:
> -			adev->ip_blocks = fiji_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
> -			break;
> -		case CHIP_TONGA:
> -			adev->ip_blocks = tonga_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
> -			break;
> -		case CHIP_POLARIS11:
> -		case CHIP_POLARIS10:
> -			adev->ip_blocks = polaris11_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
> -			break;
> -
> -		case CHIP_CARRIZO:
> -		case CHIP_STONEY:
> -			adev->ip_blocks = cz_ip_blocks_vd;
> -			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
> -			break;
> -		default:
> -			/* FIXME: not supported yet */
> -			return -EINVAL;
> -		}
> -	} else {
> -		switch (adev->asic_type) {
> -		case CHIP_TOPAZ:
> -			adev->ip_blocks = topaz_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
> -			break;
> -		case CHIP_FIJI:
> -			adev->ip_blocks = fiji_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
> -			break;
> -		case CHIP_TONGA:
> -			adev->ip_blocks = tonga_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
> -			break;
> -		case CHIP_POLARIS11:
> -		case CHIP_POLARIS10:
> -			adev->ip_blocks = polaris11_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
> -			break;
> -		case CHIP_CARRIZO:
> -		case CHIP_STONEY:
> -			adev->ip_blocks = cz_ip_blocks;
> -			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
> -			break;
> -		default:
> -			/* FIXME: not supported yet */
> -			return -EINVAL;
> -		}
> -	}
> -
> -	return 0;
> -}
> -
>   #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
>   #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
>   #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
> @@ -1985,7 +1257,7 @@ static int vi_common_set_powergating_state(void *handle,
>   	return 0;
>   }
>   
> -const struct amd_ip_funcs vi_common_ip_funcs = {
> +static const struct amd_ip_funcs vi_common_ip_funcs = {
>   	.name = "vi_common",
>   	.early_init = vi_common_early_init,
>   	.late_init = NULL,
> @@ -2002,3 +1274,110 @@ const struct amd_ip_funcs vi_common_ip_funcs = {
>   	.set_powergating_state = vi_common_set_powergating_state,
>   };
>   
> +static const struct amdgpu_ip_block_version vi_common_ip_block =
> +{
> +	.type = AMD_IP_BLOCK_TYPE_COMMON,
> +	.major = 1,
> +	.minor = 0,
> +	.rev = 0,
> +	.funcs = &vi_common_ip_funcs,
> +};
> +
> +int vi_set_ip_blocks(struct amdgpu_device *adev)
> +{
> +	switch (adev->asic_type) {
> +	case CHIP_TOPAZ:
> +		/* topaz has no DCE, UVD, VCE */
> +		amdgpu_ip_block_add(adev, &vi_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
> +		amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
> +		break;
> +	case CHIP_FIJI:
> +		amdgpu_ip_block_add(adev, &vi_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
> +		amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
> +		break;
> +	case CHIP_TONGA:
> +		amdgpu_ip_block_add(adev, &vi_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
> +		break;
> +	case CHIP_POLARIS11:
> +	case CHIP_POLARIS10:
> +		amdgpu_ip_block_add(adev, &vi_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
> +		amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
> +		break;
> +	case CHIP_CARRIZO:
> +		amdgpu_ip_block_add(adev, &vi_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &cz_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
> +#if defined(CONFIG_DRM_AMD_ACP)
> +		amdgpu_ip_block_add(adev, &acp_ip_block);
> +#endif
> +		break;
> +	case CHIP_STONEY:
> +		amdgpu_ip_block_add(adev, &vi_common_ip_block);
> +		amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
> +		amdgpu_ip_block_add(adev, &cz_ih_ip_block);
> +		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
> +		if (adev->enable_virtual_display)
> +			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
> +		else
> +			amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
> +		amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
> +		amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
> +		amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
> +		amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
> +#if defined(CONFIG_DRM_AMD_ACP)
> +		amdgpu_ip_block_add(adev, &acp_ip_block);
> +#endif
> +		break;
> +	default:
> +		/* FIXME: not supported yet */
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
> index 5020940..575d7ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.h
> @@ -24,8 +24,6 @@
>   #ifndef __VI_H__
>   #define __VI_H__
>   
> -extern const struct amd_ip_funcs vi_common_ip_funcs;
> -
>   void vi_srbm_select(struct amdgpu_device *adev,
>   		    u32 me, u32 pipe, u32 queue, u32 vmid);
>   int vi_set_ip_blocks(struct amdgpu_device *adev);