On Mon, Oct 10, 2016 at 7:23 AM, Marek Olšák <maraeo at gmail.com> wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Required for border colors in compute shaders.
>
> Signed-off-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
> drivers/gpu/drm/radeon/si.c | 1 +
> drivers/gpu/drm/radeon/sid.h | 1 +
> 3 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
> index a192653..a95263c 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -90,23 +90,24 @@
> * 2.39.0 - Add INFO query for number of active CUs
> * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
> * CS to GPU on >= r600
> * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
> * 2.42.0 - Add VCE/VUI (Video Usability Information) support
> * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
> * 2.44.0 - SET_APPEND_CNT packet3 support
> * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
> * 2.46.0 - Add PFP_SYNC_ME support on evergreen
> * 2.47.0 - Add UVD_NO_OP register support
> + * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
> */
> #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 47
> +#define KMS_DRIVER_MINOR 48
> #define KMS_DRIVER_PATCHLEVEL 0
> int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
> int radeon_driver_unload_kms(struct drm_device *dev);
> void radeon_driver_lastclose_kms(struct drm_device *dev);
> int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
> void radeon_driver_postclose_kms(struct drm_device *dev,
> struct drm_file *file_priv);
> void radeon_driver_preclose_kms(struct drm_device *dev,
> struct drm_file *file_priv);
> int radeon_suspend_kms(struct drm_device *dev, bool suspend,
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 7ee9aaf..e402be8 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -4424,20 +4424,21 @@ static bool si_vm_reg_valid(u32 reg)
> case PA_SC_LINE_STIPPLE_STATE:
> case PA_SC_ENHANCE:
> case SQC_CACHES:
> case SPI_STATIC_THREAD_MGMT_1:
> case SPI_STATIC_THREAD_MGMT_2:
> case SPI_STATIC_THREAD_MGMT_3:
> case SPI_PS_MAX_WAVE_ID:
> case SPI_CONFIG_CNTL:
> case SPI_CONFIG_CNTL_1:
> case TA_CNTL_AUX:
> + case TA_CS_BC_BASE_ADDR:
> return true;
> default:
> DRM_ERROR("Invalid register 0x%x in CS\n", reg);
> return false;
> }
> }
>
> static int si_vm_packet3_ce_check(struct radeon_device *rdev,
> u32 *ib, struct radeon_cs_packet *pkt)
> {
> diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
> index eb220ee..65a911d 100644
> --- a/drivers/gpu/drm/radeon/sid.h
> +++ b/drivers/gpu/drm/radeon/sid.h
> @@ -1138,20 +1138,21 @@
> #define CGTS_USER_TCC_DISABLE 0x914C
> #define TCC_DISABLE_MASK 0xFFFF0000
> #define TCC_DISABLE_SHIFT 16
> #define CGTS_SM_CTRL_REG 0x9150
> #define OVERRIDE (1 << 21)
> #define LS_OVERRIDE (1 << 22)
>
> #define SPI_LB_CU_MASK 0x9354
>
> #define TA_CNTL_AUX 0x9508
> +#define TA_CS_BC_BASE_ADDR 0x950C
>
> #define CC_RB_BACKEND_DISABLE 0x98F4
> #define BACKEND_DISABLE(x) ((x) << 16)
> #define GB_ADDR_CONFIG 0x98F8
> #define NUM_PIPES(x) ((x) << 0)
> #define NUM_PIPES_MASK 0x00000007
> #define NUM_PIPES_SHIFT 0
> #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
> #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
> #define PIPE_INTERLEAVE_SIZE_SHIFT 4
> --
> 2.7.4
>
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