SMU buffer is used for power feature, but for virtualization, the power is controlled by hypervisor. Ignore it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu at amd.com> Signed-off-by: Monk Liu <Monk.Liu at amd.com> --- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c index 877445d..f49b548 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c @@ -407,8 +407,14 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) 0x0); if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ - smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); - smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); + if (!cgs_is_virtualization_enabled(smumgr->device)) { + smu7_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SMU_DRAM_ADDR_HI, + smu_data->smu_buffer.mc_addr_high); + smu7_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SMU_DRAM_ADDR_LO, + smu_data->smu_buffer.mc_addr_low); + } fw_to_load = UCODE_ID_RLC_G_MASK + UCODE_ID_SDMA0_MASK + UCODE_ID_SDMA1_MASK @@ -543,7 +549,6 @@ int smu7_init(struct pp_smumgr *smumgr) smu_data = (struct smu7_smumgr *)(smumgr->backend); smu_data->header_buffer.data_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; - smu_data->smu_buffer.data_size = 200*4096; /* Allocate FW image data structure and header buffer and * send the header buffer address to SMU */ @@ -566,6 +571,10 @@ int smu7_init(struct pp_smumgr *smumgr) (cgs_handle_t)smu_data->header_buffer.handle); return -EINVAL); + if (cgs_is_virtualization_enabled(smumgr->device)) + return 0; + + smu_data->smu_buffer.data_size = 200*4096; smu_allocate_memory(smumgr->device, smu_data->smu_buffer.data_size, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, -- 2.7.4