From: Dmytro Laktyushkin <Dmytro.Laktyushkin@xxxxxxx>
Change-Id: I7f41c0582f80f7f525076654a2003edb68b0929c
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 1 -
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 7 ----
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 6 ----
.../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 39 ----------------------
.../amd/dal/dc/dce110/dce110_transform_bit_depth.h | 4 ---
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 29 ++++++++++++++++
.../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 39 +++++++++++-----------
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c | 8 -----
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h | 2 --
.../amd/dal/dc/dce80/dce80_transform_bit_depth.c | 26 ---------------
.../amd/dal/dc/dce80/dce80_transform_bit_depth.h | 2 --
.../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c | 32 ++++++++++++++++++
12 files changed, 80 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index c6c2d01a2e5b..74e1a191cfbe 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1642,7 +1642,6 @@ static void init_hw(struct core_dc *dc)
dc->hwss.enable_display_power_gating(
dc, i, bp,
PIPE_GATING_CONTROL_DISABLE);
- xfm->funcs->transform_power_up(xfm);
dc->hwss.enable_display_pipe_clock_gating(
dc->ctx,
true);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
index 492856290470..ca599959c7e2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -72,8 +72,6 @@ static void dce110_transform_reset(struct transform *xfm)
static const struct transform_funcs dce110_transform_funcs = {
.transform_reset = dce110_transform_reset,
- .transform_power_up =
- dce110_transform_power_up,
.transform_set_scaler =
dce110_transform_set_scaler,
.transform_set_gamut_remap =
@@ -113,8 +111,3 @@ bool dce110_transform_construct(
return true;
}
-
-bool dce110_transform_power_up(struct transform *xfm)
-{
- return dce110_transform_power_up_line_buffer(xfm);
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
index 7f3e50bbb4f1..afa33e4621b7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
@@ -56,17 +56,11 @@ bool dce110_transform_construct(struct dce110_transform *xfm110,
uint32_t inst,
const struct dce110_transform_reg_offsets *reg_offsets);
-bool dce110_transform_power_up(struct transform *xfm);
-
/* SCALER RELATED */
void dce110_transform_set_scaler(
struct transform *xfm,
const struct scaler_data *data);
-void dce110_transform_set_scaler_filter(
- struct transform *xfm,
- struct scaler_filter *filter);
-
/* GAMUT RELATED */
void dce110_transform_set_gamut_remap(
struct transform *xfm,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
index 966c90bab67c..84338166977f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
@@ -582,18 +582,6 @@ int32_t dce110_transform_get_max_num_of_supported_lines(
return (max_pixels_supports / pixel_width);
}
-bool dce110_transform_is_prefetch_enabled(
- struct dce110_transform *xfm110)
-{
- uint32_t value = dm_read_reg(
- xfm110->base.ctx, LB_REG(mmLB_DATA_FORMAT));
-
- if (get_reg_field_value(value, LB_DATA_FORMAT, PREFETCH) == 1)
- return true;
-
- return false;
-}
-
static void set_denormalization(
struct dce110_transform *xfm110,
enum dc_color_depth depth)
@@ -704,33 +692,6 @@ bool dce110_transform_set_pixel_storage_depth(
return ret;
}
-/* LB_MEMORY_CONFIG
- * 00 - Use all three pieces of memory
- * 01 - Use only one piece of memory of total 720x144 bits
- * 10 - Use two pieces of memory of total 960x144 bits
- * 11 - reserved
- *
- * LB_MEMORY_SIZE
- * Total entries of LB memory.
- * This number should be larger than 960. The default value is 1712(0x6B0) */
-bool dce110_transform_power_up_line_buffer(struct transform *xfm)
-{
- struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- uint32_t value;
-
- value = dm_read_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-
- /*Use all three pieces of memory always*/
- set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
- /*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, xfm110->base.lb_memory_size, LB_MEMORY_CTRL,
- LB_MEMORY_SIZE);
-
- dm_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-
- return true;
-}
-
/* Underlay pipe functions*/
bool dce110_transform_v_set_pixel_storage_depth(
struct transform *xfm,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
index a28efb049335..bb195fd43580 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
@@ -27,14 +27,10 @@
#include "dce110_transform.h"
-bool dce110_transform_power_up_line_buffer(struct transform *xfm);
-
bool dce110_transform_get_max_num_of_supported_lines(
struct transform *xfm,
enum lb_pixel_depth depth,
uint32_t pixel_width);
-bool dce110_transform_is_prefetch_enabled(
- struct dce110_transform *xfm110);
#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
index 2663abdfb5d6..7dd173ccf4b9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
@@ -501,6 +501,33 @@ static void dce110_transform_set_alpha(struct transform *xfm, bool enable)
dm_write_reg(ctx, addr, value);
}
+/* LB_MEMORY_CONFIG
+ * 00 - Use all three pieces of memory
+ * 01 - Use only one piece of memory of total 720x144 bits
+ * 10 - Use two pieces of memory of total 960x144 bits
+ * 11 - reserved
+ *
+ * LB_MEMORY_SIZE
+ * Total entries of LB memory.
+ * This number should be larger than 960. The default value is 1712(0x6B0) */
+static bool dce110_transform_power_up_line_buffer(struct transform *xfm)
+{
+ struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
+ uint32_t value;
+
+ value = dm_read_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
+
+ /*Use all three pieces of memory always*/
+ set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
+ /*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
+ set_reg_field_value(value, xfm110->base.lb_memory_size, LB_MEMORY_CTRL,
+ LB_MEMORY_SIZE);
+
+ dm_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
+
+ return true;
+}
+
void dce110_transform_set_scaler(
struct transform *xfm,
const struct scaler_data *data)
@@ -510,6 +537,8 @@ void dce110_transform_set_scaler(
bool filter_updated = false;
const uint16_t *coeffs_v, *coeffs_h;
+ dce110_transform_power_up_line_buffer(xfm);
+
disable_enhanced_sharpness(xfm110);
/* 1. Program overscan */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
index b1a8d456ca67..13b99026e662 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
@@ -501,6 +501,24 @@ static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
}
}
+static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
+{
+ struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
+ uint32_t value;
+
+ value = dm_read_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL);
+
+ /*Use all three pieces of memory always*/
+ set_reg_field_value(value, 0, LBV_MEMORY_CTRL, LB_MEMORY_CONFIG);
+ /*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
+ set_reg_field_value(value, xfm110->base.lb_memory_size, LBV_MEMORY_CTRL,
+ LB_MEMORY_SIZE);
+
+ dm_write_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL, value);
+
+ return true;
+}
+
static void dce110_transform_v_set_scaler(
struct transform *xfm,
const struct scaler_data *data)
@@ -512,6 +530,7 @@ static void dce110_transform_v_set_scaler(
struct rect luma_viewport = {0};
struct rect chroma_viewport = {0};
+ dce110_transform_v_power_up_line_buffer(xfm);
/* 1. Calculate viewport, viewport programming should happen after init
* calculations as they may require an adjustment in the viewport.
*/
@@ -587,24 +606,6 @@ static void dce110_transform_v_set_scaler(
set_coeff_update_complete(xfm110);
}
-static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
-{
- struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- uint32_t value;
-
- value = dm_read_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL);
-
- /*Use all three pieces of memory always*/
- set_reg_field_value(value, 0, LBV_MEMORY_CTRL, LB_MEMORY_CONFIG);
- /*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, xfm110->base.lb_memory_size, LBV_MEMORY_CTRL,
- LB_MEMORY_SIZE);
-
- dm_write_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL, value);
-
- return true;
-}
-
static void dce110_transform_v_reset(struct transform *xfm)
{
struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
@@ -618,8 +619,6 @@ static void dce110_transform_v_reset(struct transform *xfm)
static const struct transform_funcs dce110_transform_v_funcs = {
.transform_reset =
dce110_transform_v_reset,
- .transform_power_up =
- dce110_transform_v_power_up_line_buffer,
.transform_set_scaler =
dce110_transform_v_set_scaler,
.transform_set_gamut_remap =
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
index e99950f40439..e2187608fd62 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
@@ -62,8 +62,6 @@ static void dce80_transform_reset(struct transform *xfm)
static const struct transform_funcs dce80_transform_funcs = {
.transform_reset = dce80_transform_reset,
- .transform_power_up =
- dce80_transform_power_up,
.transform_set_scaler =
dce80_transform_set_scaler,
.transform_set_gamut_remap =
@@ -103,9 +101,3 @@ bool dce80_transform_construct(
return true;
}
-
-bool dce80_transform_power_up(struct transform *xfm)
-{
- return dce80_transform_power_up_line_buffer(xfm);
-}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
index ce625ac417df..a6217c189815 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
@@ -52,8 +52,6 @@ bool dce80_transform_construct(struct dce80_transform *xfm80,
uint32_t inst,
const struct dce80_transform_reg_offsets *offsets);
-bool dce80_transform_power_up(struct transform *xfm);
-
/* SCALER RELATED */
void dce80_transform_set_scaler(
struct transform *xfm,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
index 7d03684a4e7c..fbc4d53e027e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
@@ -675,30 +675,4 @@ bool dce80_transform_set_pixel_storage_depth(
return ret;
}
-/* LB_MEMORY_CONFIG
- * 00 - Use all three pieces of memory
- * 01 - Use only one piece of memory of total 720x144 bits
- * 10 - Use two pieces of memory of total 960x144 bits
- * 11 - reserved
- *
- * LB_MEMORY_SIZE
- * Total entries of LB memory.
- * This number should be larger than 960. The default value is 1712(0x6B0) */
-bool dce80_transform_power_up_line_buffer(struct transform *xfm)
-{
- struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- uint32_t value;
-
- value = dm_read_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-
- /*Use all three pieces of memory always*/
- set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
- /*hard coded number DCE8 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, xfm80->base.lb_memory_size, LB_MEMORY_CTRL,
- LB_MEMORY_SIZE);
-
- dm_write_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
index a8d9008a9f00..beecefba16a5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
@@ -27,8 +27,6 @@
#include "dce80_transform.h"
-bool dce80_transform_power_up_line_buffer(struct transform *xfm);
-
void dce80_transform_enable_alpha(
struct dce80_transform *xfm80,
bool enable);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
index 130af10e030d..caf4def8510f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
@@ -41,6 +41,9 @@
#define DCFE_REG(reg)\
(reg + xfm80->offsets.crtc_offset)
+#define LB_REG(reg)\
+ (reg + xfm80->offsets.lb_offset)
+
static void disable_enhanced_sharpness(struct dce80_transform *xfm80)
{
uint32_t value;
@@ -640,6 +643,33 @@ static void program_scl_ratios_inits(
dm_write_reg(xfm80->base.ctx, addr, value);
}
+/* LB_MEMORY_CONFIG
+ * 00 - Use all three pieces of memory
+ * 01 - Use only one piece of memory of total 720x144 bits
+ * 10 - Use two pieces of memory of total 960x144 bits
+ * 11 - reserved
+ *
+ * LB_MEMORY_SIZE
+ * Total entries of LB memory.
+ * This number should be larger than 960. The default value is 1712(0x6B0) */
+static bool dce80_transform_power_up_line_buffer(struct transform *xfm)
+{
+ struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
+ uint32_t value;
+
+ value = dm_read_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
+
+ /*Use all three pieces of memory always*/
+ set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
+ /*hard coded number DCE8 1712(0x6B0) Partitions: 720/960/1712*/
+ set_reg_field_value(value, xfm80->base.lb_memory_size, LB_MEMORY_CTRL,
+ LB_MEMORY_SIZE);
+
+ dm_write_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
+
+ return true;
+}
+
void dce80_transform_set_scaler(
struct transform *xfm,
const struct scaler_data *data)
@@ -648,6 +678,8 @@ void dce80_transform_set_scaler(
bool is_scaling_required;
struct dc_context *ctx = xfm->ctx;
+ dce80_transform_power_up_line_buffer(xfm);
+
{
uint32_t addr = SCL_REG(mmSCL_BYPASS_CONTROL);
uint32_t value = dm_read_reg(xfm->ctx, addr);
--
2.10.1
