From: Dmytro Laktyushkin <Dmytro.Laktyushkin@xxxxxxx>
Change-Id: Iacc1e470565f85fee6e29e249d7b0beb8ff999b9
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 35 +---
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 203 +++++++--------------
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 3 +-
3 files changed, 80 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
index 4079a64d6958..676aaa14eae8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -621,14 +621,20 @@ static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chro
return taps;
}
-bool transform_get_optimal_number_of_taps_helper(
+
+bool dce110_transform_get_optimal_number_of_taps(
struct transform *xfm,
struct scaler_data *scl_data,
- uint32_t pixel_width,
- const struct scaling_taps *in_taps) {
-
+ const struct scaling_taps *in_taps)
+{
+ struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
+ int pixel_width = scl_data->viewport.width;
int max_num_of_lines;
+ if (xfm110->prescaler_on &&
+ (scl_data->viewport.width > scl_data->recout.width))
+ pixel_width = scl_data->recout.width;
+
max_num_of_lines = dce110_transform_get_max_num_of_supported_lines(
xfm,
scl_data->lb_params.depth,
@@ -676,27 +682,6 @@ bool transform_get_optimal_number_of_taps_helper(
/* we've got valid taps */
return true;
-
-}
-
-bool dce110_transform_get_optimal_number_of_taps(
- struct transform *xfm,
- struct scaler_data *scl_data,
- const struct scaling_taps *in_taps)
-{
- struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- int pixel_width = scl_data->viewport.width;
-
- if (xfm110->prescaler_on &&
- (scl_data->viewport.width > scl_data->recout.width))
- pixel_width = scl_data->recout.width;
-
- return transform_get_optimal_number_of_taps_helper(
- xfm,
- scl_data,
- pixel_width,
- in_taps);
-
}
static void dce110_transform_reset(struct transform *xfm)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
index f8f320ff2ee5..aa7104b70152 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
@@ -142,143 +142,83 @@
XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
-#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
- XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
+#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \
+ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
+#define XFM_REG_FIELD_LIST(type) \
+ type OUT_CLAMP_MIN_B_CB; \
+ type OUT_CLAMP_MAX_B_CB; \
+ type OUT_CLAMP_MIN_G_Y; \
+ type OUT_CLAMP_MAX_G_Y; \
+ type OUT_CLAMP_MIN_R_CR; \
+ type OUT_CLAMP_MAX_R_CR; \
+ type OUT_ROUND_TRUNC_MODE; \
+ type DCP_SPATIAL_DITHER_EN; \
+ type DCP_SPATIAL_DITHER_MODE; \
+ type DCP_SPATIAL_DITHER_DEPTH; \
+ type DCP_FRAME_RANDOM_ENABLE; \
+ type DCP_RGB_RANDOM_ENABLE; \
+ type DCP_HIGHPASS_RANDOM_ENABLE; \
+ type DENORM_MODE; \
+ type PIXEL_DEPTH; \
+ type PIXEL_EXPAN_MODE; \
+ type GAMUT_REMAP_C11; \
+ type GAMUT_REMAP_C12; \
+ type GAMUT_REMAP_C13; \
+ type GAMUT_REMAP_C14; \
+ type GAMUT_REMAP_C21; \
+ type GAMUT_REMAP_C22; \
+ type GAMUT_REMAP_C23; \
+ type GAMUT_REMAP_C24; \
+ type GAMUT_REMAP_C31; \
+ type GAMUT_REMAP_C32; \
+ type GAMUT_REMAP_C33; \
+ type GAMUT_REMAP_C34; \
+ type GRPH_GAMUT_REMAP_MODE; \
+ type SCL_MODE; \
+ type SCL_PSCL_EN; \
+ type SCL_H_NUM_OF_TAPS; \
+ type SCL_V_NUM_OF_TAPS; \
+ type SCL_BOUNDARY_MODE; \
+ type EXT_OVERSCAN_LEFT; \
+ type EXT_OVERSCAN_RIGHT; \
+ type EXT_OVERSCAN_TOP; \
+ type EXT_OVERSCAN_BOTTOM; \
+ type SCL_COEFF_MEM_PWR_DIS; \
+ type SCL_COEFF_MEM_PWR_STATE; \
+ type SCL_C_RAM_FILTER_TYPE; \
+ type SCL_C_RAM_PHASE; \
+ type SCL_C_RAM_TAP_PAIR_IDX; \
+ type SCL_C_RAM_EVEN_TAP_COEF_EN; \
+ type SCL_C_RAM_EVEN_TAP_COEF; \
+ type SCL_C_RAM_ODD_TAP_COEF_EN; \
+ type SCL_C_RAM_ODD_TAP_COEF; \
+ type VIEWPORT_X_START; \
+ type VIEWPORT_Y_START; \
+ type VIEWPORT_HEIGHT; \
+ type VIEWPORT_WIDTH; \
+ type SCL_H_SCALE_RATIO; \
+ type SCL_V_SCALE_RATIO; \
+ type SCL_H_INIT_INT; \
+ type SCL_H_INIT_FRAC; \
+ type SCL_V_INIT_INT; \
+ type SCL_V_INIT_FRAC; \
+ type LB_MEMORY_CONFIG; \
+ type LB_MEMORY_SIZE; \
+ type SCL_V_2TAP_HARDCODE_COEF_EN; \
+ type SCL_H_2TAP_HARDCODE_COEF_EN; \
+ type SCL_COEF_UPDATE_COMPLETE; \
+ type ALPHA_EN
struct dce110_transform_shift {
- uint8_t OUT_CLAMP_MIN_B_CB;
- uint8_t OUT_CLAMP_MAX_B_CB;
- uint8_t OUT_CLAMP_MIN_G_Y;
- uint8_t OUT_CLAMP_MAX_G_Y;
- uint8_t OUT_CLAMP_MIN_R_CR;
- uint8_t OUT_CLAMP_MAX_R_CR;
- uint8_t OUT_ROUND_TRUNC_MODE;
- uint8_t DCP_SPATIAL_DITHER_EN;
- uint8_t DCP_SPATIAL_DITHER_MODE;
- uint8_t DCP_SPATIAL_DITHER_DEPTH;
- uint8_t DCP_FRAME_RANDOM_ENABLE;
- uint8_t DCP_RGB_RANDOM_ENABLE;
- uint8_t DCP_HIGHPASS_RANDOM_ENABLE;
- uint8_t DENORM_MODE;
- uint8_t PIXEL_DEPTH;
- uint8_t PIXEL_EXPAN_MODE;
- uint8_t GAMUT_REMAP_C11;
- uint8_t GAMUT_REMAP_C12;
- uint8_t GAMUT_REMAP_C13;
- uint8_t GAMUT_REMAP_C14;
- uint8_t GAMUT_REMAP_C21;
- uint8_t GAMUT_REMAP_C22;
- uint8_t GAMUT_REMAP_C23;
- uint8_t GAMUT_REMAP_C24;
- uint8_t GAMUT_REMAP_C31;
- uint8_t GAMUT_REMAP_C32;
- uint8_t GAMUT_REMAP_C33;
- uint8_t GAMUT_REMAP_C34;
- uint8_t GRPH_GAMUT_REMAP_MODE;
- uint8_t SCL_MODE;
- uint8_t SCL_PSCL_EN;
- uint8_t SCL_H_NUM_OF_TAPS;
- uint8_t SCL_V_NUM_OF_TAPS;
- uint8_t SCL_BOUNDARY_MODE;
- uint8_t EXT_OVERSCAN_LEFT;
- uint8_t EXT_OVERSCAN_RIGHT;
- uint8_t EXT_OVERSCAN_TOP;
- uint8_t EXT_OVERSCAN_BOTTOM;
- uint8_t SCL_COEFF_MEM_PWR_DIS;
- uint8_t SCL_COEFF_MEM_PWR_STATE;
- uint8_t SCL_C_RAM_FILTER_TYPE;
- uint8_t SCL_C_RAM_PHASE;
- uint8_t SCL_C_RAM_TAP_PAIR_IDX;
- uint8_t SCL_C_RAM_EVEN_TAP_COEF_EN;
- uint8_t SCL_C_RAM_EVEN_TAP_COEF;
- uint8_t SCL_C_RAM_ODD_TAP_COEF_EN;
- uint8_t SCL_C_RAM_ODD_TAP_COEF;
- uint8_t VIEWPORT_X_START;
- uint8_t VIEWPORT_Y_START;
- uint8_t VIEWPORT_HEIGHT;
- uint8_t VIEWPORT_WIDTH;
- uint8_t SCL_H_SCALE_RATIO;
- uint8_t SCL_V_SCALE_RATIO;
- uint8_t SCL_H_INIT_INT;
- uint8_t SCL_H_INIT_FRAC;
- uint8_t SCL_V_INIT_INT;
- uint8_t SCL_V_INIT_FRAC;
- uint8_t LB_MEMORY_CONFIG;
- uint8_t LB_MEMORY_SIZE;
- uint8_t SCL_V_2TAP_HARDCODE_COEF_EN;
- uint8_t SCL_H_2TAP_HARDCODE_COEF_EN;
- uint8_t SCL_COEF_UPDATE_COMPLETE;
- uint8_t ALPHA_EN;
+ XFM_REG_FIELD_LIST(uint8_t);
};
struct dce110_transform_mask {
- uint32_t OUT_CLAMP_MIN_B_CB;
- uint32_t OUT_CLAMP_MAX_B_CB;
- uint32_t OUT_CLAMP_MIN_G_Y;
- uint32_t OUT_CLAMP_MAX_G_Y;
- uint32_t OUT_CLAMP_MIN_R_CR;
- uint32_t OUT_CLAMP_MAX_R_CR;
- uint32_t OUT_ROUND_TRUNC_MODE;
- uint32_t DCP_SPATIAL_DITHER_EN;
- uint32_t DCP_SPATIAL_DITHER_MODE;
- uint32_t DCP_SPATIAL_DITHER_DEPTH;
- uint32_t DCP_FRAME_RANDOM_ENABLE;
- uint32_t DCP_RGB_RANDOM_ENABLE;
- uint32_t DCP_HIGHPASS_RANDOM_ENABLE;
- uint32_t DENORM_MODE;
- uint32_t PIXEL_DEPTH;
- uint32_t PIXEL_EXPAN_MODE;
- uint32_t GAMUT_REMAP_C11;
- uint32_t GAMUT_REMAP_C12;
- uint32_t GAMUT_REMAP_C13;
- uint32_t GAMUT_REMAP_C14;
- uint32_t GAMUT_REMAP_C21;
- uint32_t GAMUT_REMAP_C22;
- uint32_t GAMUT_REMAP_C23;
- uint32_t GAMUT_REMAP_C24;
- uint32_t GAMUT_REMAP_C31;
- uint32_t GAMUT_REMAP_C32;
- uint32_t GAMUT_REMAP_C33;
- uint32_t GAMUT_REMAP_C34;
- uint32_t GRPH_GAMUT_REMAP_MODE;
- uint32_t SCL_MODE;
- uint32_t SCL_PSCL_EN;
- uint32_t SCL_H_NUM_OF_TAPS;
- uint32_t SCL_V_NUM_OF_TAPS;
- uint32_t SCL_BOUNDARY_MODE;
- uint32_t EXT_OVERSCAN_LEFT;
- uint32_t EXT_OVERSCAN_RIGHT;
- uint32_t EXT_OVERSCAN_TOP;
- uint32_t EXT_OVERSCAN_BOTTOM;
- uint32_t SCL_COEFF_MEM_PWR_DIS;
- uint32_t SCL_COEFF_MEM_PWR_STATE;
- uint32_t SCL_C_RAM_FILTER_TYPE;
- uint32_t SCL_C_RAM_PHASE;
- uint32_t SCL_C_RAM_TAP_PAIR_IDX;
- uint32_t SCL_C_RAM_EVEN_TAP_COEF_EN;
- uint32_t SCL_C_RAM_EVEN_TAP_COEF;
- uint32_t SCL_C_RAM_ODD_TAP_COEF_EN;
- uint32_t SCL_C_RAM_ODD_TAP_COEF;
- uint32_t VIEWPORT_X_START;
- uint32_t VIEWPORT_Y_START;
- uint32_t VIEWPORT_HEIGHT;
- uint32_t VIEWPORT_WIDTH;
- uint32_t SCL_H_SCALE_RATIO;
- uint32_t SCL_V_SCALE_RATIO;
- uint32_t SCL_H_INIT_INT;
- uint32_t SCL_H_INIT_FRAC;
- uint32_t SCL_V_INIT_INT;
- uint32_t SCL_V_INIT_FRAC;
- uint32_t LB_MEMORY_CONFIG;
- uint32_t LB_MEMORY_SIZE;
- uint32_t SCL_V_2TAP_HARDCODE_COEF_EN;
- uint32_t SCL_H_2TAP_HARDCODE_COEF_EN;
- uint32_t SCL_COEF_UPDATE_COMPLETE;
- uint32_t ALPHA_EN;
+ XFM_REG_FIELD_LIST(uint32_t);
};
struct dce110_transform_registers {
@@ -317,16 +257,9 @@ struct dce110_transform_registers {
uint32_t LB_MEMORY_CTRL;
uint32_t SCL_UPDATE;
};
-struct dce110_transform_reg_offsets {
- uint32_t scl_offset;
- uint32_t dcfe_offset;
- uint32_t dcp_offset;
- uint32_t lb_offset;
-};
struct dce110_transform {
struct transform base;
- struct dce110_transform_reg_offsets offsets;
const struct dce110_transform_registers *regs;
const struct dce110_transform_shift *xfm_shift;
const struct dce110_transform_mask *xfm_mask;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
index 31972312f3eb..db2be4bc639c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
@@ -128,6 +128,7 @@ static void program_multi_taps_filter(
phase 0 is unique and phase N/2 is unique if N is even*/
for (pair = 0; pair < taps_pairs; pair++) {
uint16_t odd_coeff = 0;
+ uint16_t even_coeff = coeffs[array_idx];
REG_SET_3(SCL_COEF_RAM_SELECT, 0,
SCL_C_RAM_FILTER_TYPE, filter_type,
@@ -143,7 +144,7 @@ static void program_multi_taps_filter(
REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
SCL_C_RAM_EVEN_TAP_COEF_EN, 1,
- SCL_C_RAM_EVEN_TAP_COEF, coeffs[array_idx],
+ SCL_C_RAM_EVEN_TAP_COEF, even_coeff,
SCL_C_RAM_ODD_TAP_COEF_EN, 1,
SCL_C_RAM_ODD_TAP_COEF, odd_coeff);
}
--
2.10.1
