From: Dmytro Laktyushkin <Dmytro.Laktyushkin@xxxxxxx>
Change-Id: Ifabf0fe703a72b9e599ef1066027dbecaf5ae080
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 67 ++-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 45 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 540 +++++----------------
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 296 ++++++++++-
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 442 +++--------------
.../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 267 +++-------
.../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h | 1 +
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 68 +--
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h | 2 +-
.../amd/dal/dc/dce80/dce80_transform_bit_depth.c | 31 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h | 98 ++--
11 files changed, 681 insertions(+), 1176 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 4c19d2f3849d..951d8fb31914 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -179,41 +179,6 @@ static const struct dce110_clk_src_reg_offsets dce100_clk_src_reg_offsets[] = {
}
};
-static const struct dce110_transform_reg_offsets dce100_xfm_offsets[] = {
-{
- .scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{
- .scl_offset = (mmSCL3_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB3_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL4_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB4_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL5_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB5_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-}
-};
-
static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
{
.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
@@ -245,6 +210,29 @@ static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
+
+#define transform_regs(id)\
+[id] = {\
+ XFM_COMMON_REG_LIST_DCE100(id)\
+}
+
+static const struct dce110_transform_registers xfm_regs[] = {
+ transform_regs(0),
+ transform_regs(1),
+ transform_regs(2),
+ transform_regs(3),
+ transform_regs(4),
+ transform_regs(5)
+};
+
+static const struct dce110_transform_shift xfm_shift = {
+ XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce110_transform_mask xfm_mask = {
+ XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
+
#define aux_regs(id)\
[id] = {\
AUX_REG_LIST(id)\
@@ -534,8 +522,7 @@ static void dce100_transform_destroy(struct transform **xfm)
static struct transform *dce100_transform_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_transform_reg_offsets *offsets)
+ uint32_t inst)
{
struct dce110_transform *transform =
dm_alloc(sizeof(struct dce110_transform));
@@ -543,7 +530,8 @@ static struct transform *dce100_transform_create(
if (!transform)
return NULL;
- if (dce110_transform_construct(transform, ctx, inst, offsets)) {
+ if (dce110_transform_construct(transform, ctx, inst,
+ &xfm_regs[inst], &xfm_shift, &xfm_mask)) {
transform->base.lb_memory_size = 0x6B0; /*1712*/
return &transform->base;
}
@@ -1030,8 +1018,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.transforms[i] = dce100_transform_create(
- ctx, i, &dce100_xfm_offsets[i]);
+ pool->base.transforms[i] = dce100_transform_create(ctx, i);
if (pool->base.transforms[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 961aa3f26999..802e22f263b3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -149,24 +149,6 @@ static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
}
};
-static const struct dce110_transform_reg_offsets dce110_xfm_offsets[] = {
-{
- .scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-}
-};
static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
{
@@ -201,6 +183,24 @@ static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
.reg_name = mm ## block ## id ## _ ## reg_name
+#define transform_regs(id)\
+[id] = {\
+ XFM_COMMON_REG_LIST_DCE110(id)\
+}
+
+static const struct dce110_transform_registers xfm_regs[] = {
+ transform_regs(0),
+ transform_regs(1),
+ transform_regs(2)
+};
+
+static const struct dce110_transform_shift xfm_shift = {
+ XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce110_transform_mask xfm_mask = {
+ XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
#define aux_regs(id)\
[id] = {\
@@ -512,8 +512,7 @@ static void dce110_transform_destroy(struct transform **xfm)
static struct transform *dce110_transform_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_transform_reg_offsets *offsets)
+ uint32_t inst)
{
struct dce110_transform *transform =
dm_alloc(sizeof(struct dce110_transform));
@@ -521,7 +520,8 @@ static struct transform *dce110_transform_create(
if (!transform)
return NULL;
- if (dce110_transform_construct(transform, ctx, inst, offsets))
+ if (dce110_transform_construct(transform, ctx, inst,
+ &xfm_regs[inst], &xfm_shift, &xfm_mask))
return &transform->base;
BREAK_TO_DEBUGGER();
@@ -1336,8 +1336,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.transforms[i] = dce110_transform_create(
- ctx, i, &dce110_xfm_offsets[i]);
+ pool->base.transforms[i] = dce110_transform_create(ctx, i);
if (pool->base.transforms[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
index 73e1861f96fc..02a29f3cc5d5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -25,9 +25,6 @@
#include "dm_services.h"
-/* include DCE11 register header files */
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
#include "dc_types.h"
#include "core_types.h"
@@ -39,46 +36,21 @@
#include "dce110_transform.h"
+#include "reg_helper.h"
-#define DCP_REG(reg)\
- (reg + xfm110->offsets.dcp_offset)
+#define REG(reg) \
+ (xfm110->regs->reg)
-#define LB_REG(reg)\
- (reg + xfm110->offsets.lb_offset)
+#undef FN
+#define FN(reg_name, field_name) \
+ xfm110->xfm_shift->field_name, xfm110->xfm_mask->field_name
+
+#define CTX \
+ xfm110->base.ctx
#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
#define GAMUT_MATRIX_SIZE 12
-#define DISP_BRIGHTNESS_DEFAULT_HW 0
-#define DISP_BRIGHTNESS_MIN_HW -25
-#define DISP_BRIGHTNESS_MAX_HW 25
-#define DISP_BRIGHTNESS_STEP_HW 1
-#define DISP_BRIGHTNESS_HW_DIVIDER 100
-
-#define DISP_HUE_DEFAULT_HW 0
-#define DISP_HUE_MIN_HW -30
-#define DISP_HUE_MAX_HW 30
-#define DISP_HUE_STEP_HW 1
-#define DISP_HUE_HW_DIVIDER 1
-
-#define DISP_CONTRAST_DEFAULT_HW 100
-#define DISP_CONTRAST_MIN_HW 50
-#define DISP_CONTRAST_MAX_HW 150
-#define DISP_CONTRAST_STEP_HW 1
-#define DISP_CONTRAST_HW_DIVIDER 100
-
-#define DISP_SATURATION_DEFAULT_HW 100
-#define DISP_SATURATION_MIN_HW 0
-#define DISP_SATURATION_MAX_HW 200
-#define DISP_SATURATION_STEP_HW 1
-#define DISP_SATURATION_HW_DIVIDER 100
-
-#define DISP_KELVIN_DEGRES_DEFAULT 6500
-#define DISP_KELVIN_DEGRES_MIN 4000
-#define DISP_KELVIN_DEGRES_MAX 10000
-#define DISP_KELVIN_DEGRES_STEP 100
-#define DISP_KELVIN_HW_DIVIDER 10000
-
enum dcp_out_trunc_round_mode {
DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
DCP_OUT_TRUNC_ROUND_MODE_ROUND
@@ -116,8 +88,7 @@ enum dcp_spatial_dither_depth {
DCP_SPATIAL_DITHER_DEPTH_24BPP
};
-/**
- *******************************************************************************
+/*****************************************************************************
* set_clamp
*
* @param depth : bit depth to set the clamp to (should match denorm)
@@ -125,16 +96,12 @@ enum dcp_spatial_dither_depth {
* @brief
* Programs clamp according to panel bit depth.
*
- * @return
- * true if succeeds
- *
- *******************************************************************************
- */
-static bool set_clamp(
+ *******************************************************************************/
+static void set_clamp(
struct dce110_transform *xfm110,
enum dc_color_depth depth)
{
- uint32_t clamp_max = 0;
+ int clamp_max = 0;
/* At the clamp block the data will be MSB aligned, so we set the max
* clamp accordingly.
@@ -159,75 +126,23 @@ static bool set_clamp(
clamp_max = 0x3FFF;
break;
default:
- ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
- return false;
- }
-
- {
- uint32_t value = 0;
- /* always set min to 0 */
- set_reg_field_value(
- value,
- 0,
- OUT_CLAMP_CONTROL_B_CB,
- OUT_CLAMP_MIN_B_CB);
-
- set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_B_CB,
- OUT_CLAMP_MAX_B_CB);
-
- dm_write_reg(xfm110->base.ctx,
- DCP_REG(mmOUT_CLAMP_CONTROL_B_CB),
- value);
- }
-
- {
- uint32_t value = 0;
- /* always set min to 0 */
- set_reg_field_value(
- value,
- 0,
- OUT_CLAMP_CONTROL_G_Y,
- OUT_CLAMP_MIN_G_Y);
-
- set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_G_Y,
- OUT_CLAMP_MAX_G_Y);
-
- dm_write_reg(xfm110->base.ctx,
- DCP_REG(mmOUT_CLAMP_CONTROL_G_Y),
- value);
+ clamp_max = 0x3FC0;
+ BREAK_TO_DEBUGGER(); /* Invalid clamp bit depth */
}
+ REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0,
+ OUT_CLAMP_MIN_B_CB, 0,
+ OUT_CLAMP_MAX_B_CB, clamp_max);
- {
- uint32_t value = 0;
- /* always set min to 0 */
- set_reg_field_value(
- value,
- 0,
- OUT_CLAMP_CONTROL_R_CR,
- OUT_CLAMP_MIN_R_CR);
+ REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0,
+ OUT_CLAMP_MIN_G_Y, 0,
+ OUT_CLAMP_MAX_G_Y, clamp_max);
- set_reg_field_value(
- value,
- clamp_max,
- OUT_CLAMP_CONTROL_R_CR,
- OUT_CLAMP_MAX_R_CR);
-
- dm_write_reg(xfm110->base.ctx,
- DCP_REG(mmOUT_CLAMP_CONTROL_R_CR),
- value);
- }
-
- return true;
+ REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0,
+ OUT_CLAMP_MIN_R_CR, 0,
+ OUT_CLAMP_MAX_R_CR, clamp_max);
}
-/**
- *******************************************************************************
+/*******************************************************************************
* set_round
*
* @brief
@@ -258,19 +173,14 @@ static bool set_clamp(
14 - round to u0.14
15 - round to u0.13
- * @return
- * true if succeeds.
- *******************************************************************************
- */
-static bool set_round(
+ ******************************************************************************/
+static void set_round(
struct dce110_transform *xfm110,
enum dcp_out_trunc_round_mode mode,
enum dcp_out_trunc_round_depth depth)
{
- uint32_t depth_bits = 0;
- uint32_t mode_bit = 0;
- /* zero out all bits */
- uint32_t value = 0;
+ int depth_bits = 0;
+ int mode_bit = 0;
/* set up bit depth */
switch (depth) {
@@ -296,17 +206,10 @@ static bool set_round(
depth_bits = 4;
break;
default:
- /* Invalid dcp_out_trunc_round_depth */
- ASSERT_CRITICAL(false);
- return false;
+ depth_bits = 4;
+ BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_depth */
}
- set_reg_field_value(
- value,
- depth_bits,
- OUT_ROUND_CONTROL,
- OUT_ROUND_TRUNC_MODE);
-
/* set up round or truncate */
switch (mode) {
case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
@@ -316,29 +219,15 @@ static bool set_round(
mode_bit = 1;
break;
default:
- /* Invalid dcp_out_trunc_round_mode */
- ASSERT_CRITICAL(false);
- return false;
+ BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_mode */
}
depth_bits |= mode_bit << 3;
- set_reg_field_value(
- value,
- depth_bits,
- OUT_ROUND_CONTROL,
- OUT_ROUND_TRUNC_MODE);
-
- /* write the register */
- dm_write_reg(xfm110->base.ctx,
- DCP_REG(mmOUT_ROUND_CONTROL),
- value);
-
- return true;
+ REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);
}
-/**
- *******************************************************************************
+/*****************************************************************************
* set_dither
*
* @brief
@@ -351,12 +240,9 @@ static bool set_round(
* @param [in] rgb_random_enable : enable rgb random
* @param [in] highpass_random_enable : enable highpass random
*
- * @return
- * true if succeeds.
- *******************************************************************************
- */
+ ******************************************************************************/
-static bool set_dither(
+static void set_dither(
struct dce110_transform *xfm110,
bool dither_enable,
enum dcp_spatial_dither_mode dither_mode,
@@ -365,18 +251,8 @@ static bool set_dither(
bool rgb_random_enable,
bool highpass_random_enable)
{
- uint32_t dither_depth_bits = 0;
- uint32_t dither_mode_bits = 0;
- /* zero out all bits */
- uint32_t value = 0;
-
- /* set up the fields */
- if (dither_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_SPATIAL_DITHER_EN);
+ int dither_depth_bits = 0;
+ int dither_mode_bits = 0;
switch (dither_mode) {
case DCP_SPATIAL_DITHER_MODE_AAAA:
@@ -393,15 +269,8 @@ static bool set_dither(
break;
default:
/* Invalid dcp_spatial_dither_mode */
- ASSERT_CRITICAL(false);
- return false;
-
+ BREAK_TO_DEBUGGER();
}
- set_reg_field_value(
- value,
- dither_mode_bits,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_SPATIAL_DITHER_MODE);
switch (dither_depth) {
case DCP_SPATIAL_DITHER_DEPTH_30BPP:
@@ -412,47 +281,20 @@ static bool set_dither(
break;
default:
/* Invalid dcp_spatial_dither_depth */
- ASSERT_CRITICAL(false);
- return false;
+ BREAK_TO_DEBUGGER();
}
- set_reg_field_value(
- value,
- dither_depth_bits,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_SPATIAL_DITHER_DEPTH);
-
- if (frame_random_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_FRAME_RANDOM_ENABLE);
-
- if (rgb_random_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_RGB_RANDOM_ENABLE);
-
- if (highpass_random_enable)
- set_reg_field_value(
- value,
- 1,
- DCP_SPATIAL_DITHER_CNTL,
- DCP_HIGHPASS_RANDOM_ENABLE);
-
/* write the register */
- dm_write_reg(xfm110->base.ctx,
- DCP_REG(mmDCP_SPATIAL_DITHER_CNTL),
- value);
-
- return true;
+ REG_SET_6(DCP_SPATIAL_DITHER_CNTL, 0,
+ DCP_SPATIAL_DITHER_EN, dither_enable,
+ DCP_SPATIAL_DITHER_MODE, dither_mode_bits,
+ DCP_SPATIAL_DITHER_DEPTH, dither_depth_bits,
+ DCP_FRAME_RANDOM_ENABLE, frame_random_enable,
+ DCP_RGB_RANDOM_ENABLE, rgb_random_enable,
+ DCP_HIGHPASS_RANDOM_ENABLE, highpass_random_enable);
}
-/**
- *******************************************************************************
+/*****************************************************************************
* dce110_transform_bit_depth_reduction_program
*
* @brief
@@ -461,11 +303,8 @@ static bool set_dither(
*
* @param depth : bit depth to set the clamp to (should match denorm)
*
- * @return
- * true if succeeds.
- *******************************************************************************
- */
-static bool program_bit_depth_reduction(
+ ******************************************************************************/
+static void program_bit_depth_reduction(
struct dce110_transform *xfm110,
enum dc_color_depth depth,
const struct bit_depth_reduction_params *bit_depth_params)
@@ -476,10 +315,7 @@ static bool program_bit_depth_reduction(
bool rgb_random_enable;
bool highpass_random_enable;
- if (depth > COLOR_DEPTH_121212) {
- ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
- return false;
- }
+ ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
if (bit_depth_params->flags.SPATIAL_DITHER_ENABLED) {
depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
@@ -496,11 +332,7 @@ static bool program_bit_depth_reduction(
spatial_dither_mode = DCP_SPATIAL_DITHER_MODE_A_AA_A;
- if (!set_clamp(xfm110, depth)) {
- /* Failure in set_clamp() */
- ASSERT_CRITICAL(false);
- return false;
- }
+ set_clamp(xfm110, depth);
switch (depth_reduction_mode) {
case DCP_BIT_DEPTH_REDUCTION_MODE_DITHER:
@@ -548,11 +380,9 @@ static bool program_bit_depth_reduction(
break;
default:
/* Invalid DCP Depth reduction mode */
- ASSERT_CRITICAL(false);
+ BREAK_TO_DEBUGGER();
break;
}
-
- return true;
}
static int dce110_transform_get_max_num_of_supported_lines(
@@ -563,7 +393,7 @@ static int dce110_transform_get_max_num_of_supported_lines(
int pixels_per_entries = 0;
int max_pixels_supports = 0;
- ASSERT_CRITICAL(pixel_width);
+ ASSERT(pixel_width);
/* Find number of pixels that can fit into a single LB entry and
* take floor of the value since we cannot store a single pixel
@@ -589,11 +419,11 @@ static int dce110_transform_get_max_num_of_supported_lines(
dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Invalid LB pixel depth",
__func__);
- ASSERT_CRITICAL(false);
+ BREAK_TO_DEBUGGER();
break;
}
- ASSERT_CRITICAL(pixels_per_entries);
+ ASSERT(pixels_per_entries);
max_pixels_supports =
pixels_per_entries *
@@ -606,42 +436,25 @@ static void set_denormalization(
struct dce110_transform *xfm110,
enum dc_color_depth depth)
{
- uint32_t value = dm_read_reg(xfm110->base.ctx,
- DCP_REG(mmDENORM_CONTROL));
+ int denorm_mode = 0;
switch (depth) {
case COLOR_DEPTH_666:
/* 63/64 for 6 bit output color depth */
- set_reg_field_value(
- value,
- 1,
- DENORM_CONTROL,
- DENORM_MODE);
+ denorm_mode = 1;
break;
case COLOR_DEPTH_888:
/* Unity for 8 bit output color depth
* because prescale is disabled by default */
- set_reg_field_value(
- value,
- 0,
- DENORM_CONTROL,
- DENORM_MODE);
+ denorm_mode = 0;
break;
case COLOR_DEPTH_101010:
/* 1023/1024 for 10 bit output color depth */
- set_reg_field_value(
- value,
- 3,
- DENORM_CONTROL,
- DENORM_MODE);
+ denorm_mode = 3;
break;
case COLOR_DEPTH_121212:
/* 4095/4096 for 12 bit output color depth */
- set_reg_field_value(
- value,
- 5,
- DENORM_CONTROL,
- DENORM_MODE);
+ denorm_mode = 5;
break;
case COLOR_DEPTH_141414:
case COLOR_DEPTH_161616:
@@ -650,215 +463,90 @@ static void set_denormalization(
break;
}
- dm_write_reg(xfm110->base.ctx,
- DCP_REG(mmDENORM_CONTROL),
- value);
-
+ REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);
}
-bool dce110_transform_set_pixel_storage_depth(
+static void dce110_transform_set_pixel_storage_depth(
struct transform *xfm,
enum lb_pixel_depth depth,
const struct bit_depth_reduction_params *bit_depth_params)
{
struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- bool ret = true;
- uint32_t value;
+ int pixel_depth, expan_mode;
enum dc_color_depth color_depth;
- value = dm_read_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT));
switch (depth) {
case LB_PIXEL_DEPTH_18BPP:
color_depth = COLOR_DEPTH_666;
- set_reg_field_value(value, 2, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ pixel_depth = 2;
+ expan_mode = 1;
break;
case LB_PIXEL_DEPTH_24BPP:
color_depth = COLOR_DEPTH_888;
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ pixel_depth = 1;
+ expan_mode = 1;
break;
case LB_PIXEL_DEPTH_30BPP:
color_depth = COLOR_DEPTH_101010;
- set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ pixel_depth = 0;
+ expan_mode = 1;
break;
case LB_PIXEL_DEPTH_36BPP:
color_depth = COLOR_DEPTH_121212;
- set_reg_field_value(value, 3, LB_DATA_FORMAT, PIXEL_DEPTH);
- set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ pixel_depth = 3;
+ expan_mode = 0;
break;
default:
- ret = false;
+ color_depth = COLOR_DEPTH_101010;
+ pixel_depth = 0;
+ expan_mode = 1;
+ BREAK_TO_DEBUGGER();
break;
}
- if (ret == true) {
- set_denormalization(xfm110, color_depth);
- ret = program_bit_depth_reduction(xfm110, color_depth,
- bit_depth_params);
-
- set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
- dm_write_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
- if (!(xfm110->lb_pixel_depth_supported & depth)) {
- /*we should use unsupported capabilities
- * unless it is required by w/a*/
- dm_logger_write(xfm->ctx->logger, LOG_WARNING,
- "%s: Capability not supported",
- __func__);
- }
- }
+ set_denormalization(xfm110, color_depth);
+ program_bit_depth_reduction(xfm110, color_depth, bit_depth_params);
+
+ REG_UPDATE_2(LB_DATA_FORMAT,
+ PIXEL_DEPTH, pixel_depth,
+ PIXEL_EXPAN_MODE, expan_mode);
- return ret;
+ if (!(xfm110->lb_pixel_depth_supported & depth)) {
+ /*we should use unsupported capabilities
+ * unless it is required by w/a*/
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
+ "%s: Capability not supported",
+ __func__);
+ }
}
static void program_gamut_remap(
struct dce110_transform *xfm110,
const uint16_t *reg_val)
{
- struct dc_context *ctx = xfm110->base.ctx;
- uint32_t value = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-
- /* the register controls ovl also */
- value = dm_read_reg(ctx, addr);
-
if (reg_val) {
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C11_C12);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[0],
- GAMUT_REMAP_C11_C12,
- GAMUT_REMAP_C11);
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[1],
- GAMUT_REMAP_C11_C12,
- GAMUT_REMAP_C12);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C13_C14);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[2],
- GAMUT_REMAP_C13_C14,
- GAMUT_REMAP_C13);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[3],
- GAMUT_REMAP_C13_C14,
- GAMUT_REMAP_C14);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C21_C22);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[4],
- GAMUT_REMAP_C21_C22,
- GAMUT_REMAP_C21);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[5],
- GAMUT_REMAP_C21_C22,
- GAMUT_REMAP_C22);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C23_C24);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[6],
- GAMUT_REMAP_C23_C24,
- GAMUT_REMAP_C23);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[7],
- GAMUT_REMAP_C23_C24,
- GAMUT_REMAP_C24);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C31_C32);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[8],
- GAMUT_REMAP_C31_C32,
- GAMUT_REMAP_C31);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[9],
- GAMUT_REMAP_C31_C32,
- GAMUT_REMAP_C32);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C33_C34);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[10],
- GAMUT_REMAP_C33_C34,
- GAMUT_REMAP_C33);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[11],
- GAMUT_REMAP_C33_C34,
- GAMUT_REMAP_C34);
-
- dm_write_reg(ctx, addr, reg_data);
- }
-
- set_reg_field_value(
- value,
- 1,
- GAMUT_REMAP_CONTROL,
- GRPH_GAMUT_REMAP_MODE);
-
+ REG_SET_2(GAMUT_REMAP_C11_C12, 0,
+ GAMUT_REMAP_C11, reg_val[0],
+ GAMUT_REMAP_C12, reg_val[1]);
+ REG_SET_2(GAMUT_REMAP_C13_C14, 0,
+ GAMUT_REMAP_C13, reg_val[2],
+ GAMUT_REMAP_C14, reg_val[3]);
+ REG_SET_2(GAMUT_REMAP_C21_C22, 0,
+ GAMUT_REMAP_C21, reg_val[4],
+ GAMUT_REMAP_C22, reg_val[5]);
+ REG_SET_2(GAMUT_REMAP_C23_C24, 0,
+ GAMUT_REMAP_C23, reg_val[6],
+ GAMUT_REMAP_C24, reg_val[7]);
+ REG_SET_2(GAMUT_REMAP_C31_C32, 0,
+ GAMUT_REMAP_C31, reg_val[8],
+ GAMUT_REMAP_C32, reg_val[9]);
+ REG_SET_2(GAMUT_REMAP_C33_C34, 0,
+ GAMUT_REMAP_C33, reg_val[10],
+ GAMUT_REMAP_C34, reg_val[11]);
+
+ REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1);
} else
- set_reg_field_value(
- value,
- 0,
- GAMUT_REMAP_CONTROL,
- GRPH_GAMUT_REMAP_MODE);
-
- addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
- dm_write_reg(ctx, addr, value);
+ REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0);
}
@@ -1041,14 +729,18 @@ bool dce110_transform_construct(
struct dce110_transform *xfm110,
struct dc_context *ctx,
uint32_t inst,
- const struct dce110_transform_reg_offsets *reg_offsets)
+ const struct dce110_transform_registers *regs,
+ const struct dce110_transform_shift *xfm_shift,
+ const struct dce110_transform_mask *xfm_mask)
{
xfm110->base.ctx = ctx;
xfm110->base.inst = inst;
xfm110->base.funcs = &dce110_transform_funcs;
- xfm110->offsets = *reg_offsets;
+ xfm110->regs = regs;
+ xfm110->xfm_shift = xfm_shift;
+ xfm110->xfm_mask = xfm_mask;
xfm110->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
index 9fb1decd1e65..d1f53816b4c5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
@@ -33,6 +33,290 @@
#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
#define LB_BITS_PER_ENTRY 144
+#define XFM_COMMON_REG_LIST_DCE_BASE(id) \
+ SRI(LB_DATA_FORMAT, LB, id), \
+ SRI(GAMUT_REMAP_CONTROL, DCP, id), \
+ SRI(GAMUT_REMAP_C11_C12, DCP, id), \
+ SRI(GAMUT_REMAP_C13_C14, DCP, id), \
+ SRI(GAMUT_REMAP_C21_C22, DCP, id), \
+ SRI(GAMUT_REMAP_C23_C24, DCP, id), \
+ SRI(GAMUT_REMAP_C31_C32, DCP, id), \
+ SRI(GAMUT_REMAP_C33_C34, DCP, id), \
+ SRI(DENORM_CONTROL, DCP, id), \
+ SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
+ SRI(OUT_ROUND_CONTROL, DCP, id), \
+ SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
+ SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
+ SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
+ SRI(SCL_MODE, SCL, id), \
+ SRI(SCL_TAP_CONTROL, SCL, id), \
+ SRI(SCL_CONTROL, SCL, id), \
+ SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
+ SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
+ SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
+ SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
+ SRI(SCL_COEF_RAM_SELECT, SCL, id), \
+ SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
+ SRI(VIEWPORT_START, SCL, id), \
+ SRI(VIEWPORT_SIZE, SCL, id), \
+ SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
+ SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
+ SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
+ SRI(SCL_VERT_FILTER_INIT, SCL, id), \
+ SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
+ SRI(LB_MEMORY_CTRL, LB, id), \
+ SRI(SCL_UPDATE, SCL, id)
+
+#define XFM_COMMON_REG_LIST_DCE100(id) \
+ XFM_COMMON_REG_LIST_DCE_BASE(id), \
+ SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
+ SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
+
+#define XFM_COMMON_REG_LIST_DCE110(id) \
+ XFM_COMMON_REG_LIST_DCE_BASE(id), \
+ SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
+ SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
+
+#define XFM_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
+ XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
+ XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
+ XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
+ XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
+ XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
+ XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
+ XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
+ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
+ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
+ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
+ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
+ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
+ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
+ XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
+ XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
+ XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
+ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
+ XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
+ XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
+ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh), \
+ XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
+ XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
+ XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
+ XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
+ XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
+ XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
+ XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
+ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
+ XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
+ XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
+ XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
+ XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
+ XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
+ XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
+ XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
+ XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
+ XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
+ XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
+ XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
+ XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
+ XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
+ XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
+ XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
+ XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
+
+#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
+ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
+ XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
+ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh)
+
+
+struct dce110_transform_shift {
+ uint8_t OUT_CLAMP_MIN_B_CB;
+ uint8_t OUT_CLAMP_MAX_B_CB;
+ uint8_t OUT_CLAMP_MIN_G_Y;
+ uint8_t OUT_CLAMP_MAX_G_Y;
+ uint8_t OUT_CLAMP_MIN_R_CR;
+ uint8_t OUT_CLAMP_MAX_R_CR;
+ uint8_t OUT_ROUND_TRUNC_MODE;
+ uint8_t DCP_SPATIAL_DITHER_EN;
+ uint8_t DCP_SPATIAL_DITHER_MODE;
+ uint8_t DCP_SPATIAL_DITHER_DEPTH;
+ uint8_t DCP_FRAME_RANDOM_ENABLE;
+ uint8_t DCP_RGB_RANDOM_ENABLE;
+ uint8_t DCP_HIGHPASS_RANDOM_ENABLE;
+ uint8_t DENORM_MODE;
+ uint8_t PIXEL_DEPTH;
+ uint8_t PIXEL_EXPAN_MODE;
+ uint8_t GAMUT_REMAP_C11;
+ uint8_t GAMUT_REMAP_C12;
+ uint8_t GAMUT_REMAP_C13;
+ uint8_t GAMUT_REMAP_C14;
+ uint8_t GAMUT_REMAP_C21;
+ uint8_t GAMUT_REMAP_C22;
+ uint8_t GAMUT_REMAP_C23;
+ uint8_t GAMUT_REMAP_C24;
+ uint8_t GAMUT_REMAP_C31;
+ uint8_t GAMUT_REMAP_C32;
+ uint8_t GAMUT_REMAP_C33;
+ uint8_t GAMUT_REMAP_C34;
+ uint8_t GRPH_GAMUT_REMAP_MODE;
+ uint8_t SCL_MODE;
+ uint8_t SCL_PSCL_EN;
+ uint8_t SCL_H_NUM_OF_TAPS;
+ uint8_t SCL_V_NUM_OF_TAPS;
+ uint8_t SCL_BOUNDARY_MODE;
+ uint8_t EXT_OVERSCAN_LEFT;
+ uint8_t EXT_OVERSCAN_RIGHT;
+ uint8_t EXT_OVERSCAN_TOP;
+ uint8_t EXT_OVERSCAN_BOTTOM;
+ uint8_t SCL_COEFF_MEM_PWR_DIS;
+ uint8_t SCL_COEFF_MEM_PWR_STATE;
+ uint8_t SCL_C_RAM_FILTER_TYPE;
+ uint8_t SCL_C_RAM_PHASE;
+ uint8_t SCL_C_RAM_TAP_PAIR_IDX;
+ uint8_t SCL_C_RAM_EVEN_TAP_COEF_EN;
+ uint8_t SCL_C_RAM_EVEN_TAP_COEF;
+ uint8_t SCL_C_RAM_ODD_TAP_COEF_EN;
+ uint8_t SCL_C_RAM_ODD_TAP_COEF;
+ uint8_t VIEWPORT_X_START;
+ uint8_t VIEWPORT_Y_START;
+ uint8_t VIEWPORT_HEIGHT;
+ uint8_t VIEWPORT_WIDTH;
+ uint8_t SCL_H_SCALE_RATIO;
+ uint8_t SCL_V_SCALE_RATIO;
+ uint8_t SCL_H_INIT_INT;
+ uint8_t SCL_H_INIT_FRAC;
+ uint8_t SCL_V_INIT_INT;
+ uint8_t SCL_V_INIT_FRAC;
+ uint8_t LB_MEMORY_CONFIG;
+ uint8_t LB_MEMORY_SIZE;
+ uint8_t SCL_V_2TAP_HARDCODE_COEF_EN;
+ uint8_t SCL_H_2TAP_HARDCODE_COEF_EN;
+ uint8_t SCL_COEF_UPDATE_COMPLETE;
+ uint8_t ALPHA_EN;
+};
+
+struct dce110_transform_mask {
+ uint32_t OUT_CLAMP_MIN_B_CB;
+ uint32_t OUT_CLAMP_MAX_B_CB;
+ uint32_t OUT_CLAMP_MIN_G_Y;
+ uint32_t OUT_CLAMP_MAX_G_Y;
+ uint32_t OUT_CLAMP_MIN_R_CR;
+ uint32_t OUT_CLAMP_MAX_R_CR;
+ uint32_t OUT_ROUND_TRUNC_MODE;
+ uint32_t DCP_SPATIAL_DITHER_EN;
+ uint32_t DCP_SPATIAL_DITHER_MODE;
+ uint32_t DCP_SPATIAL_DITHER_DEPTH;
+ uint32_t DCP_FRAME_RANDOM_ENABLE;
+ uint32_t DCP_RGB_RANDOM_ENABLE;
+ uint32_t DCP_HIGHPASS_RANDOM_ENABLE;
+ uint32_t DENORM_MODE;
+ uint32_t PIXEL_DEPTH;
+ uint32_t PIXEL_EXPAN_MODE;
+ uint32_t GAMUT_REMAP_C11;
+ uint32_t GAMUT_REMAP_C12;
+ uint32_t GAMUT_REMAP_C13;
+ uint32_t GAMUT_REMAP_C14;
+ uint32_t GAMUT_REMAP_C21;
+ uint32_t GAMUT_REMAP_C22;
+ uint32_t GAMUT_REMAP_C23;
+ uint32_t GAMUT_REMAP_C24;
+ uint32_t GAMUT_REMAP_C31;
+ uint32_t GAMUT_REMAP_C32;
+ uint32_t GAMUT_REMAP_C33;
+ uint32_t GAMUT_REMAP_C34;
+ uint32_t GRPH_GAMUT_REMAP_MODE;
+ uint32_t SCL_MODE;
+ uint32_t SCL_PSCL_EN;
+ uint32_t SCL_H_NUM_OF_TAPS;
+ uint32_t SCL_V_NUM_OF_TAPS;
+ uint32_t SCL_BOUNDARY_MODE;
+ uint32_t EXT_OVERSCAN_LEFT;
+ uint32_t EXT_OVERSCAN_RIGHT;
+ uint32_t EXT_OVERSCAN_TOP;
+ uint32_t EXT_OVERSCAN_BOTTOM;
+ uint32_t SCL_COEFF_MEM_PWR_DIS;
+ uint32_t SCL_COEFF_MEM_PWR_STATE;
+ uint32_t SCL_C_RAM_FILTER_TYPE;
+ uint32_t SCL_C_RAM_PHASE;
+ uint32_t SCL_C_RAM_TAP_PAIR_IDX;
+ uint32_t SCL_C_RAM_EVEN_TAP_COEF_EN;
+ uint32_t SCL_C_RAM_EVEN_TAP_COEF;
+ uint32_t SCL_C_RAM_ODD_TAP_COEF_EN;
+ uint32_t SCL_C_RAM_ODD_TAP_COEF;
+ uint32_t VIEWPORT_X_START;
+ uint32_t VIEWPORT_Y_START;
+ uint32_t VIEWPORT_HEIGHT;
+ uint32_t VIEWPORT_WIDTH;
+ uint32_t SCL_H_SCALE_RATIO;
+ uint32_t SCL_V_SCALE_RATIO;
+ uint32_t SCL_H_INIT_INT;
+ uint32_t SCL_H_INIT_FRAC;
+ uint32_t SCL_V_INIT_INT;
+ uint32_t SCL_V_INIT_FRAC;
+ uint32_t LB_MEMORY_CONFIG;
+ uint32_t LB_MEMORY_SIZE;
+ uint32_t SCL_V_2TAP_HARDCODE_COEF_EN;
+ uint32_t SCL_H_2TAP_HARDCODE_COEF_EN;
+ uint32_t SCL_COEF_UPDATE_COMPLETE;
+ uint32_t ALPHA_EN;
+};
+
+struct dce110_transform_registers {
+ uint32_t LB_DATA_FORMAT;
+ uint32_t GAMUT_REMAP_CONTROL;
+ uint32_t GAMUT_REMAP_C11_C12;
+ uint32_t GAMUT_REMAP_C13_C14;
+ uint32_t GAMUT_REMAP_C21_C22;
+ uint32_t GAMUT_REMAP_C23_C24;
+ uint32_t GAMUT_REMAP_C31_C32;
+ uint32_t GAMUT_REMAP_C33_C34;
+ uint32_t DENORM_CONTROL;
+ uint32_t DCP_SPATIAL_DITHER_CNTL;
+ uint32_t OUT_ROUND_CONTROL;
+ uint32_t OUT_CLAMP_CONTROL_R_CR;
+ uint32_t OUT_CLAMP_CONTROL_G_Y;
+ uint32_t OUT_CLAMP_CONTROL_B_CB;
+ uint32_t SCL_MODE;
+ uint32_t SCL_TAP_CONTROL;
+ uint32_t SCL_CONTROL;
+ uint32_t EXT_OVERSCAN_LEFT_RIGHT;
+ uint32_t EXT_OVERSCAN_TOP_BOTTOM;
+ uint32_t SCL_VERT_FILTER_CONTROL;
+ uint32_t SCL_HORZ_FILTER_CONTROL;
+ uint32_t DCFE_MEM_PWR_CTRL;
+ uint32_t DCFE_MEM_PWR_STATUS;
+ uint32_t SCL_COEF_RAM_SELECT;
+ uint32_t SCL_COEF_RAM_TAP_DATA;
+ uint32_t VIEWPORT_START;
+ uint32_t VIEWPORT_SIZE;
+ uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
+ uint32_t SCL_VERT_FILTER_SCALE_RATIO;
+ uint32_t SCL_HORZ_FILTER_INIT;
+ uint32_t SCL_VERT_FILTER_INIT;
+ uint32_t SCL_AUTOMATIC_MODE_CONTROL;
+ uint32_t LB_MEMORY_CTRL;
+ uint32_t SCL_UPDATE;
+};
struct dce110_transform_reg_offsets {
uint32_t scl_offset;
uint32_t dcfe_offset;
@@ -43,6 +327,9 @@ struct dce110_transform_reg_offsets {
struct dce110_transform {
struct transform base;
struct dce110_transform_reg_offsets offsets;
+ const struct dce110_transform_registers *regs;
+ const struct dce110_transform_shift *xfm_shift;
+ const struct dce110_transform_mask *xfm_mask;
const uint16_t *filter_v;
const uint16_t *filter_h;
@@ -54,12 +341,9 @@ struct dce110_transform {
bool dce110_transform_construct(struct dce110_transform *xfm110,
struct dc_context *ctx,
uint32_t inst,
- const struct dce110_transform_reg_offsets *reg_offsets);
-
-bool dce110_transform_set_pixel_storage_depth(
- struct transform *xfm,
- enum lb_pixel_depth depth,
- const struct bit_depth_reduction_params *bit_depth_params);
+ const struct dce110_transform_registers *regs,
+ const struct dce110_transform_shift *xfm_shift,
+ const struct dce110_transform_mask *xfm_mask);
void dce110_transform_set_scaler(
struct transform *xfm,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
index 1f0f890023fe..31972312f3eb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
@@ -24,140 +24,60 @@
*/
#include "dm_services.h"
-
-/* include DCE11 register header files */
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-
+#include "reg_helper.h"
#include "dce110_transform.h"
-#define UP_SCALER_RATIO_MAX 16000
-#define DOWN_SCALER_RATIO_MAX 250
-#define SCALER_RATIO_DIVIDER 1000
-
-#define SCL_REG(reg)\
- (reg + xfm110->offsets.scl_offset)
-
-#define DCFE_REG(reg)\
- (reg + xfm110->offsets.dcfe_offset)
-
-#define LB_REG(reg)\
- (reg + xfm110->offsets.lb_offset)
-
#define SCL_PHASES 16
+#define REG(reg) \
+ (xfm110->regs->reg)
-static void disable_enhanced_sharpness(struct dce110_transform *xfm110)
-{
- uint32_t value;
-
- value = dm_read_reg(xfm110->base.ctx,
- SCL_REG(mmSCL_F_SHARP_CONTROL));
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_HF_SHARP_EN);
+#undef FN
+#define FN(reg_name, field_name) \
+ xfm110->xfm_shift->field_name, xfm110->xfm_mask->field_name
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_VF_SHARP_EN);
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_HF_SHARP_SCALE_FACTOR);
-
- set_reg_field_value(value, 0,
- SCL_F_SHARP_CONTROL, SCL_VF_SHARP_SCALE_FACTOR);
-
- dm_write_reg(xfm110->base.ctx,
- SCL_REG(mmSCL_F_SHARP_CONTROL), value);
-}
+#define CTX \
+ xfm110->base.ctx
static void dce110_transform_set_scaler_bypass(
struct transform *xfm,
const struct scaler_data *scl_data)
{
struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- uint32_t scl_mode;
- disable_enhanced_sharpness(xfm110);
-
- scl_mode = dm_read_reg(xfm->ctx, SCL_REG(mmSCL_MODE));
- set_reg_field_value(scl_mode, 0, SCL_MODE, SCL_MODE);
- set_reg_field_value(scl_mode, 0, SCL_MODE, SCL_PSCL_EN);
- dm_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), scl_mode);
+ REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
}
-/*
- * @Function:
- * void setup_scaling_configuration
- * @Purpose: setup scaling mode : bypass, RGb, YCbCr and number of taps
- * @Input: data
- *
- * @Output: void
- */
static bool setup_scaling_configuration(
struct dce110_transform *xfm110,
const struct scaler_data *data)
{
struct dc_context *ctx = xfm110->base.ctx;
- uint32_t addr;
- uint32_t value;
-
- addr = SCL_REG(mmSCL_BYPASS_CONTROL);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- 0,
- SCL_BYPASS_CONTROL,
- SCL_BYPASS_MODE);
- dm_write_reg(ctx, addr, value);
if (data->taps.h_taps + data->taps.v_taps <= 2) {
dce110_transform_set_scaler_bypass(&xfm110->base, NULL);
return false;
}
- addr = SCL_REG(mmSCL_TAP_CONTROL);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(value, data->taps.h_taps - 1,
- SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
- set_reg_field_value(value, data->taps.v_taps - 1,
- SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
- dm_write_reg(ctx, addr, value);
+ REG_SET_2(SCL_TAP_CONTROL, 0,
+ SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
+ SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
- addr = SCL_REG(mmSCL_MODE);
- value = dm_read_reg(ctx, addr);
if (data->format <= PIXEL_FORMAT_GRPH_END)
- set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
+ REG_UPDATE_2(SCL_MODE, SCL_MODE, 1, SCL_PSCL_EN, 1);
else
- set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
- set_reg_field_value(value, 1, SCL_MODE, SCL_PSCL_EN);
- dm_write_reg(ctx, addr, value);
+ REG_UPDATE_2(SCL_MODE, SCL_MODE, 2, SCL_PSCL_EN, 1);
- addr = SCL_REG(mmSCL_CONTROL);
- value = dm_read_reg(ctx, addr);
- /* 1 - Replaced out of bound pixels with edge */
- set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
- dm_write_reg(ctx, addr, value);
+ /* 1 - Replace out of bound pixels with edge */
+ REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
return true;
}
-/**
-* Function:
-* void program_overscan
-*
-* Purpose: Programs overscan border
-* Input: overscan
-*
-* Output:
- void
-*/
static void program_overscan(
struct dce110_transform *xfm110,
const struct scaler_data *data)
{
- uint32_t overscan_left_right = 0;
- uint32_t overscan_top_bottom = 0;
-
int overscan_right = data->h_active
- data->recout.x - data->recout.width;
int overscan_bottom = data->v_active
@@ -172,67 +92,12 @@ static void program_overscan(
overscan_bottom = 0;
}
- set_reg_field_value(overscan_left_right, data->recout.x,
- EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-
- set_reg_field_value(overscan_left_right, overscan_right,
- EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-
- set_reg_field_value(overscan_top_bottom, data->recout.y,
- EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-
- set_reg_field_value(overscan_top_bottom, overscan_bottom,
- EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-
- dm_write_reg(xfm110->base.ctx,
- SCL_REG(mmEXT_OVERSCAN_LEFT_RIGHT),
- overscan_left_right);
-
- dm_write_reg(xfm110->base.ctx,
- SCL_REG(mmEXT_OVERSCAN_TOP_BOTTOM),
- overscan_top_bottom);
-}
-
-static void program_two_taps_filter(
- struct dce110_transform *xfm110,
- bool enable,
- bool vertical)
-{
- uint32_t addr;
- uint32_t value;
- /* 1: Hard coded 2 tap filter
- * 0: Programmable 2 tap filter from coefficient RAM
- */
- if (vertical) {
- addr = SCL_REG(mmSCL_VERT_FILTER_CONTROL);
- value = dm_read_reg(xfm110->base.ctx, addr);
- set_reg_field_value(
- value,
- enable ? 1 : 0,
- SCL_VERT_FILTER_CONTROL,
- SCL_V_2TAP_HARDCODE_COEF_EN);
-
- } else {
- addr = SCL_REG(mmSCL_HORZ_FILTER_CONTROL);
- value = dm_read_reg(xfm110->base.ctx, addr);
- set_reg_field_value(
- value,
- enable ? 1 : 0,
- SCL_HORZ_FILTER_CONTROL,
- SCL_H_2TAP_HARDCODE_COEF_EN);
- }
-
- dm_write_reg(xfm110->base.ctx, addr, value);
-}
-
-static void set_coeff_update_complete(struct dce110_transform *xfm110)
-{
- uint32_t value;
- uint32_t addr = SCL_REG(mmSCL_UPDATE);
-
- value = dm_read_reg(xfm110->base.ctx, addr);
- set_reg_field_value(value, 1, SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
- dm_write_reg(xfm110->base.ctx, addr, value);
+ REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0,
+ EXT_OVERSCAN_LEFT, data->recout.x,
+ EXT_OVERSCAN_RIGHT, overscan_right);
+ REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0,
+ EXT_OVERSCAN_TOP, data->recout.y,
+ EXT_OVERSCAN_BOTTOM, overscan_bottom);
}
static void program_multi_taps_filter(
@@ -241,120 +106,65 @@ static void program_multi_taps_filter(
const uint16_t *coeffs,
enum ram_filter_type filter_type)
{
- struct dc_context *ctx = xfm110->base.ctx;
- int i, phase, pair;
+ int phase, pair;
int array_idx = 0;
int taps_pairs = (taps + 1) / 2;
int phases_to_program = SCL_PHASES / 2 + 1;
- uint32_t select = 0;
- uint32_t power_ctl, power_ctl_off;
+ uint32_t power_ctl = 0;
if (!coeffs)
return;
/*We need to disable power gating on coeff memory to do programming*/
- power_ctl = dm_read_reg(ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
- power_ctl_off = power_ctl;
- set_reg_field_value(power_ctl_off, 1, DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS);
- dm_write_reg(ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), power_ctl_off);
-
- /*Wait to disable gating:*/
- for (i = 0; i < 10; i++) {
- if (get_reg_field_value(
- dm_read_reg(ctx, DCFE_REG(mmDCFE_MEM_PWR_STATUS)),
- DCFE_MEM_PWR_STATUS,
- SCL_COEFF_MEM_PWR_STATE) == 0)
- break;
-
- udelay(1);
- }
-
- set_reg_field_value(select, filter_type, SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE);
+ if (REG(DCFE_MEM_PWR_CTRL)) {
+ power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
+ REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
+ REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);
+ }
for (phase = 0; phase < phases_to_program; phase++) {
/*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror
phase 0 is unique and phase N/2 is unique if N is even*/
- set_reg_field_value(select, phase, SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE);
for (pair = 0; pair < taps_pairs; pair++) {
- uint32_t data = 0;
-
- set_reg_field_value(select, pair,
- SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX);
-
- dm_write_reg(ctx, SCL_REG(mmSCL_COEF_RAM_SELECT), select);
-
- set_reg_field_value(
- data, 1,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_EVEN_TAP_COEF_EN);
- set_reg_field_value(
- data, coeffs[array_idx],
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_EVEN_TAP_COEF);
-
- if (taps % 2 && pair == taps_pairs - 1) {
- set_reg_field_value(
- data, 0,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF_EN);
- array_idx++;
- } else {
- set_reg_field_value(
- data, 1,
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF_EN);
- set_reg_field_value(
- data, coeffs[array_idx + 1],
- SCL_COEF_RAM_TAP_DATA,
- SCL_C_RAM_ODD_TAP_COEF);
+ uint16_t odd_coeff = 0;
+
+ REG_SET_3(SCL_COEF_RAM_SELECT, 0,
+ SCL_C_RAM_FILTER_TYPE, filter_type,
+ SCL_C_RAM_PHASE, phase,
+ SCL_C_RAM_TAP_PAIR_IDX, pair);
+ if (taps % 2 && pair == taps_pairs - 1)
+ array_idx++;
+ else {
+ odd_coeff = coeffs[array_idx + 1];
array_idx += 2;
}
- dm_write_reg(ctx, SCL_REG(mmSCL_COEF_RAM_TAP_DATA), data);
+ REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
+ SCL_C_RAM_EVEN_TAP_COEF_EN, 1,
+ SCL_C_RAM_EVEN_TAP_COEF, coeffs[array_idx],
+ SCL_C_RAM_ODD_TAP_COEF_EN, 1,
+ SCL_C_RAM_ODD_TAP_COEF, odd_coeff);
}
}
/*We need to restore power gating on coeff memory to initial state*/
- dm_write_reg(ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), power_ctl);
+ if (REG(DCFE_MEM_PWR_CTRL))
+ REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
}
static void program_viewport(
struct dce110_transform *xfm110,
const struct rect *view_port)
{
- struct dc_context *ctx = xfm110->base.ctx;
- uint32_t value = 0;
- uint32_t addr = 0;
-
- addr = SCL_REG(mmVIEWPORT_START);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- view_port->x,
- VIEWPORT_START,
- VIEWPORT_X_START);
- set_reg_field_value(
- value,
- view_port->y,
- VIEWPORT_START,
- VIEWPORT_Y_START);
- dm_write_reg(ctx, addr, value);
-
- addr = SCL_REG(mmVIEWPORT_SIZE);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(
- value,
- view_port->height,
- VIEWPORT_SIZE,
- VIEWPORT_HEIGHT);
- set_reg_field_value(
- value,
- view_port->width,
- VIEWPORT_SIZE,
- VIEWPORT_WIDTH);
- dm_write_reg(ctx, addr, value);
+ REG_SET_2(VIEWPORT_START, 0,
+ VIEWPORT_X_START, view_port->x,
+ VIEWPORT_Y_START, view_port->y);
+
+ REG_SET_2(VIEWPORT_SIZE, 0,
+ VIEWPORT_HEIGHT, view_port->height,
+ VIEWPORT_WIDTH, view_port->width);
/* TODO: add stereo support */
}
@@ -395,66 +205,22 @@ static void program_scl_ratios_inits(
struct dce110_transform *xfm110,
struct scl_ratios_inits *inits)
{
- uint32_t addr = SCL_REG(mmSCL_HORZ_FILTER_SCALE_RATIO);
- uint32_t value = 0;
-
- set_reg_field_value(
- value,
- inits->h_int_scale_ratio,
- SCL_HORZ_FILTER_SCALE_RATIO,
- SCL_H_SCALE_RATIO);
- dm_write_reg(xfm110->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_VERT_FILTER_SCALE_RATIO);
- value = 0;
- set_reg_field_value(
- value,
- inits->v_int_scale_ratio,
- SCL_VERT_FILTER_SCALE_RATIO,
- SCL_V_SCALE_RATIO);
- dm_write_reg(xfm110->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_HORZ_FILTER_INIT);
- value = 0;
- set_reg_field_value(
- value,
- inits->h_init.integer,
- SCL_HORZ_FILTER_INIT,
- SCL_H_INIT_INT);
- set_reg_field_value(
- value,
- inits->h_init.fraction,
- SCL_HORZ_FILTER_INIT,
- SCL_H_INIT_FRAC);
- dm_write_reg(xfm110->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_VERT_FILTER_INIT);
- value = 0;
- set_reg_field_value(
- value,
- inits->v_init.integer,
- SCL_VERT_FILTER_INIT,
- SCL_V_INIT_INT);
- set_reg_field_value(
- value,
- inits->v_init.fraction,
- SCL_VERT_FILTER_INIT,
- SCL_V_INIT_FRAC);
- dm_write_reg(xfm110->base.ctx, addr, value);
-
- addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
- value = 0;
- set_reg_field_value(
- value,
- 0,
- SCL_AUTOMATIC_MODE_CONTROL,
- SCL_V_CALC_AUTO_RATIO_EN);
- set_reg_field_value(
- value,
- 0,
- SCL_AUTOMATIC_MODE_CONTROL,
- SCL_H_CALC_AUTO_RATIO_EN);
- dm_write_reg(xfm110->base.ctx, addr, value);
+
+ REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
+ SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
+
+ REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
+ SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
+
+ REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
+ SCL_H_INIT_INT, inits->h_init.integer,
+ SCL_H_INIT_FRAC, inits->h_init.fraction);
+
+ REG_SET_2(SCL_VERT_FILTER_INIT, 0,
+ SCL_V_INIT_INT, inits->v_init.integer,
+ SCL_V_INIT_FRAC, inits->v_init.fraction);
+
+ REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
}
static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
@@ -474,59 +240,6 @@ static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
}
}
-
-static void dce110_transform_set_alpha(struct transform *xfm, bool enable)
-{
- struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- struct dc_context *ctx = xfm->ctx;
- uint32_t value;
- uint32_t addr = LB_REG(mmLB_DATA_FORMAT);
-
- value = dm_read_reg(ctx, addr);
-
- if (enable == 1)
- set_reg_field_value(
- value,
- 1,
- LB_DATA_FORMAT,
- ALPHA_EN);
- else
- set_reg_field_value(
- value,
- 0,
- LB_DATA_FORMAT,
- ALPHA_EN);
-
- dm_write_reg(ctx, addr, value);
-}
-
-/* LB_MEMORY_CONFIG
- * 00 - Use all three pieces of memory
- * 01 - Use only one piece of memory of total 720x144 bits
- * 10 - Use two pieces of memory of total 960x144 bits
- * 11 - reserved
- *
- * LB_MEMORY_SIZE
- * Total entries of LB memory.
- * This number should be larger than 960. The default value is 1712(0x6B0) */
-static bool dce110_transform_power_up_line_buffer(struct transform *xfm)
-{
- struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- uint32_t value;
-
- value = dm_read_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-
- /*Use all three pieces of memory always*/
- set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
- /*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, xfm110->base.lb_memory_size, LB_MEMORY_CTRL,
- LB_MEMORY_SIZE);
-
- dm_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-
- return true;
-}
-
void dce110_transform_set_scaler(
struct transform *xfm,
const struct scaler_data *data)
@@ -536,9 +249,10 @@ void dce110_transform_set_scaler(
bool filter_updated = false;
const uint16_t *coeffs_v, *coeffs_h;
- dce110_transform_power_up_line_buffer(xfm);
-
- disable_enhanced_sharpness(xfm110);
+ /*Use all three pieces of memory always*/
+ REG_SET_2(LB_MEMORY_CTRL, 0,
+ LB_MEMORY_CONFIG, 0,
+ LB_MEMORY_SIZE, xfm110->base.lb_memory_size);
/* 1. Program overscan */
program_overscan(xfm110, data);
@@ -560,7 +274,8 @@ void dce110_transform_set_scaler(
if (coeffs_v != xfm110->filter_v || coeffs_h != xfm110->filter_h) {
/* 4. Program vertical filters */
if (xfm110->filter_v == NULL)
- program_two_taps_filter(xfm110, 0, true);
+ REG_SET(SCL_VERT_FILTER_CONTROL, 0,
+ SCL_V_2TAP_HARDCODE_COEF_EN, 0);
program_multi_taps_filter(
xfm110,
data->taps.v_taps,
@@ -574,7 +289,8 @@ void dce110_transform_set_scaler(
/* 5. Program horizontal filters */
if (xfm110->filter_h == NULL)
- program_two_taps_filter(xfm110, 0, false);
+ REG_SET(SCL_HORZ_FILTER_CONTROL, 0,
+ SCL_H_2TAP_HARDCODE_COEF_EN, 0);
program_multi_taps_filter(
xfm110,
data->taps.h_taps,
@@ -597,7 +313,7 @@ void dce110_transform_set_scaler(
/* 7. Set bit to flip to new coefficient memory */
if (filter_updated)
- set_coeff_update_complete(xfm110);
+ REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);
- dce110_transform_set_alpha(xfm, data->lb_params.alpha_en);
+ REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
index 5acf14c10a10..845859d2f102 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
@@ -26,9 +26,6 @@
#include "dc_types.h"
#include "core_types.h"
-
-#include "basics/conversion.h"
-#include "dce110_transform.h"
#include "dce110_transform_v.h"
#include "dce/dce_11_0_d.h"
@@ -36,11 +33,6 @@
#define SCLV_PHASES 64
-#define DCP_REG(reg)\
- (reg + xfm110->offsets.dcp_offset)
-
-#define GAMUT_MATRIX_SIZE 12
-
struct sclv_ratios_inits {
uint32_t h_int_scale_ratio_luma;
uint32_t h_int_scale_ratio_chroma;
@@ -504,7 +496,7 @@ static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
}
}
-static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
+static bool dce110_xfmv_power_up_line_buffer(struct transform *xfm)
{
struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
uint32_t value;
@@ -522,7 +514,7 @@ static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
return true;
}
-static void dce110_transform_v_set_scaler(
+static void dce110_xfmv_set_scaler(
struct transform *xfm,
const struct scaler_data *data)
{
@@ -533,7 +525,7 @@ static void dce110_transform_v_set_scaler(
struct rect luma_viewport = {0};
struct rect chroma_viewport = {0};
- dce110_transform_v_power_up_line_buffer(xfm);
+ dce110_xfmv_power_up_line_buffer(xfm);
/* 1. Calculate viewport, viewport programming should happen after init
* calculations as they may require an adjustment in the viewport.
*/
@@ -609,7 +601,7 @@ static void dce110_transform_v_set_scaler(
set_coeff_update_complete(xfm110);
}
-static void dce110_transform_v_reset(struct transform *xfm)
+static void dce110_xfmv_reset(struct transform *xfm)
{
struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
@@ -619,213 +611,74 @@ static void dce110_transform_v_reset(struct transform *xfm)
xfm110->filter_v_c = NULL;
}
-static void program_gamut_remap(
- struct dce110_transform *xfm110,
- const uint16_t *reg_val)
+static void dce110_xfmv_set_gamut_remap(
+ struct transform *xfm,
+ const struct xfm_grph_csc_adjustment *adjust)
{
- struct dc_context *ctx = xfm110->base.ctx;
- uint32_t value = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-
- /* the register controls ovl also */
- value = dm_read_reg(ctx, addr);
-
- if (reg_val) {
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C11_C12);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[0],
- GAMUT_REMAP_C11_C12,
- GAMUT_REMAP_C11);
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[1],
- GAMUT_REMAP_C11_C12,
- GAMUT_REMAP_C12);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C13_C14);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[2],
- GAMUT_REMAP_C13_C14,
- GAMUT_REMAP_C13);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[3],
- GAMUT_REMAP_C13_C14,
- GAMUT_REMAP_C14);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C21_C22);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[4],
- GAMUT_REMAP_C21_C22,
- GAMUT_REMAP_C21);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[5],
- GAMUT_REMAP_C21_C22,
- GAMUT_REMAP_C22);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C23_C24);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[6],
- GAMUT_REMAP_C23_C24,
- GAMUT_REMAP_C23);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[7],
- GAMUT_REMAP_C23_C24,
- GAMUT_REMAP_C24);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C31_C32);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[8],
- GAMUT_REMAP_C31_C32,
- GAMUT_REMAP_C31);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[9],
- GAMUT_REMAP_C31_C32,
- GAMUT_REMAP_C32);
-
- dm_write_reg(ctx, addr, reg_data);
- }
- {
- uint32_t reg_data = 0;
- uint32_t addr = DCP_REG(mmGAMUT_REMAP_C33_C34);
-
- /* fixed S2.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[10],
- GAMUT_REMAP_C33_C34,
- GAMUT_REMAP_C33);
-
- /* fixed S0.13 format */
- set_reg_field_value(
- reg_data,
- reg_val[11],
- GAMUT_REMAP_C33_C34,
- GAMUT_REMAP_C34);
-
- dm_write_reg(ctx, addr, reg_data);
- }
-
- set_reg_field_value(
- value,
- 1,
- GAMUT_REMAP_CONTROL,
- GRPH_GAMUT_REMAP_MODE);
-
- } else
- set_reg_field_value(
- value,
- 0,
- GAMUT_REMAP_CONTROL,
- GRPH_GAMUT_REMAP_MODE);
-
- addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
- dm_write_reg(ctx, addr, value);
-
+ /* DO NOTHING*/
}
-/**
- *****************************************************************************
- * Function: dal_transform_wide_gamut_set_gamut_remap
- *
- * @param [in] const struct xfm_grph_csc_adjustment *adjust
- *
- * @return
- * void
- *
- * @note calculate and apply color temperature adjustment to in Rgb color space
- *
- * @see
- *
- *****************************************************************************
- */
-void dce110_transform_v_set_gamut_remap(
+static void dce110_xfmv_set_pixel_storage_depth(
struct transform *xfm,
- const struct xfm_grph_csc_adjustment *adjust)
+ enum lb_pixel_depth depth,
+ const struct bit_depth_reduction_params *bit_depth_params)
{
struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
+ int pixel_depth, expan_mode;
+ uint32_t reg_data = 0;
+
+ switch (depth) {
+ case LB_PIXEL_DEPTH_18BPP:
+ pixel_depth = 2;
+ expan_mode = 1;
+ break;
+ case LB_PIXEL_DEPTH_24BPP:
+ pixel_depth = 1;
+ expan_mode = 1;
+ break;
+ case LB_PIXEL_DEPTH_30BPP:
+ pixel_depth = 0;
+ expan_mode = 1;
+ break;
+ case LB_PIXEL_DEPTH_36BPP:
+ pixel_depth = 3;
+ expan_mode = 0;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
- if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
- /* Bypass if type is bypass or hw */
- program_gamut_remap(xfm110, NULL);
- else {
- struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE];
- uint16_t arr_reg_val[GAMUT_MATRIX_SIZE];
-
- arr_matrix[0] = adjust->temperature_matrix[0];
- arr_matrix[1] = adjust->temperature_matrix[1];
- arr_matrix[2] = adjust->temperature_matrix[2];
- arr_matrix[3] = dal_fixed31_32_zero;
-
- arr_matrix[4] = adjust->temperature_matrix[3];
- arr_matrix[5] = adjust->temperature_matrix[4];
- arr_matrix[6] = adjust->temperature_matrix[5];
- arr_matrix[7] = dal_fixed31_32_zero;
-
- arr_matrix[8] = adjust->temperature_matrix[6];
- arr_matrix[9] = adjust->temperature_matrix[7];
- arr_matrix[10] = adjust->temperature_matrix[8];
- arr_matrix[11] = dal_fixed31_32_zero;
-
- convert_float_matrix(
- arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
+ set_reg_field_value(
+ reg_data,
+ expan_mode,
+ LBV_DATA_FORMAT,
+ PIXEL_EXPAN_MODE);
- program_gamut_remap(xfm110, arr_reg_val);
+ set_reg_field_value(
+ reg_data,
+ pixel_depth,
+ LBV_DATA_FORMAT,
+ PIXEL_DEPTH);
+
+ dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data);
+
+ if (!(xfm110->lb_pixel_depth_supported & depth)) {
+ /*we should use unsupported capabilities
+ * unless it is required by w/a*/
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
+ "%s: Capability not supported",
+ __func__);
}
}
-static const struct transform_funcs dce110_transform_v_funcs = {
- .transform_reset = dce110_transform_v_reset,
- .transform_set_scaler = dce110_transform_v_set_scaler,
+static const struct transform_funcs dce110_xfmv_funcs = {
+ .transform_reset = dce110_xfmv_reset,
+ .transform_set_scaler = dce110_xfmv_set_scaler,
.transform_set_gamut_remap =
- dce110_transform_v_set_gamut_remap,
+ dce110_xfmv_set_gamut_remap,
.transform_set_pixel_storage_depth =
- dce110_transform_set_pixel_storage_depth,
+ dce110_xfmv_set_pixel_storage_depth,
.transform_get_optimal_number_of_taps =
dce110_transform_get_optimal_number_of_taps
};
@@ -839,7 +692,7 @@ bool dce110_transform_v_construct(
{
xfm110->base.ctx = ctx;
- xfm110->base.funcs = &dce110_transform_v_funcs;
+ xfm110->base.funcs = &dce110_xfmv_funcs;
xfm110->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
index c71f19cf94cd..c5dd2b1e8e1d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
@@ -26,6 +26,7 @@
#define __DAL_TRANSFORM_V_DCE110_H__
#include "transform.h"
+#include "dce110_transform.h"
#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
#define LB_BITS_PER_ENTRY 144
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 054f918185fc..defc067d9236 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -103,41 +103,6 @@ enum dce112_clk_src_array_id {
DCE112_CLK_SRC_TOTAL
};
-static const struct dce110_transform_reg_offsets dce112_xfm_offsets[] = {
-{
- .scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{
- .scl_offset = (mmSCL3_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB3_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL4_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB4_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-},
-{ .scl_offset = (mmSCL5_SCL_CONTROL - mmSCL_CONTROL),
- .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- .dcp_offset = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .lb_offset = (mmLB5_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-}
-};
-
static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
{
.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
@@ -240,6 +205,28 @@ static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
+#define transform_regs(id)\
+[id] = {\
+ XFM_COMMON_REG_LIST_DCE110(id)\
+}
+
+static const struct dce110_transform_registers xfm_regs[] = {
+ transform_regs(0),
+ transform_regs(1),
+ transform_regs(2),
+ transform_regs(3),
+ transform_regs(4),
+ transform_regs(5)
+};
+
+static const struct dce110_transform_shift xfm_shift = {
+ XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce110_transform_mask xfm_mask = {
+ XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
+
#define aux_regs(id)\
[id] = {\
AUX_REG_LIST(id)\
@@ -559,8 +546,7 @@ static void dce112_transform_destroy(struct transform **xfm)
static struct transform *dce112_transform_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_transform_reg_offsets *offsets)
+ uint32_t inst)
{
struct dce110_transform *transform =
dm_alloc(sizeof(struct dce110_transform));
@@ -568,7 +554,8 @@ static struct transform *dce112_transform_create(
if (!transform)
return NULL;
- if (dce110_transform_construct(transform, ctx, inst, offsets)) {
+ if (dce110_transform_construct(transform, ctx, inst,
+ &xfm_regs[inst], &xfm_shift, &xfm_mask)) {
transform->base.lb_memory_size = 0x1404; /*5124*/
return &transform->base;
}
@@ -1373,10 +1360,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.transforms[i] = dce112_transform_create(
- ctx,
- i,
- &dce112_xfm_offsets[i]);
+ pool->base.transforms[i] = dce112_transform_create(ctx, i);
if (pool->base.transforms[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
index a6217c189815..92299e36e3dd 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
@@ -67,7 +67,7 @@ void dce80_transform_set_gamut_remap(
const struct xfm_grph_csc_adjustment *adjust);
/* BIT DEPTH RELATED */
-bool dce80_transform_set_pixel_storage_depth(
+void dce80_transform_set_pixel_storage_depth(
struct transform *xfm,
enum lb_pixel_depth depth,
const struct bit_depth_reduction_params *bit_depth_params);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
index fbc4d53e027e..e74f7cfb0fe9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
@@ -617,13 +617,12 @@ static void set_denormalization(
}
-bool dce80_transform_set_pixel_storage_depth(
+void dce80_transform_set_pixel_storage_depth(
struct transform *xfm,
enum lb_pixel_depth depth,
const struct bit_depth_reduction_params *bit_depth_params)
{
struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- bool ret = true;
uint32_t value;
enum dc_color_depth color_depth;
@@ -652,27 +651,21 @@ bool dce80_transform_set_pixel_storage_depth(
set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
break;
default:
- ret = false;
break;
}
- if (ret == true) {
- set_denormalization(xfm80, color_depth);
- ret = program_bit_depth_reduction(xfm80, color_depth);
-
- set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
- dm_write_reg(
- xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
- if (!(xfm80->lb_pixel_depth_supported & depth)) {
- /*we should use unsupported capabilities
- * unless it is required by w/a*/
- dm_logger_write(xfm->ctx->logger, LOG_WARNING,
- "%s: Capability not supported",
- __func__);
- }
+ set_denormalization(xfm80, color_depth);
+ program_bit_depth_reduction(xfm80, color_depth);
+
+ set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
+ dm_write_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
+ if (!(xfm80->lb_pixel_depth_supported & depth)) {
+ /*we should use unsupported capabilities
+ * unless it is required by w/a*/
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
+ "%s: Capability not supported",
+ __func__);
}
-
- return ret;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
index bf112892d35e..82c788af90f2 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
@@ -52,69 +52,68 @@ enum lb_pixel_depth {
};
enum raw_gamma_ramp_type {
- GAMMA_RAMP_TYPE_UNINITIALIZED,
- GAMMA_RAMP_TYPE_DEFAULT,
- GAMMA_RAMP_TYPE_RGB256,
- GAMMA_RAMP_TYPE_FIXED_POINT
+ GAMMA_RAMP_TYPE_UNINITIALIZED,
+ GAMMA_RAMP_TYPE_DEFAULT,
+ GAMMA_RAMP_TYPE_RGB256,
+ GAMMA_RAMP_TYPE_FIXED_POINT
};
#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
/* Colorimetry */
enum colorimetry {
- COLORIMETRY_NO_DATA = 0,
- COLORIMETRY_ITU601 = 1,
- COLORIMETRY_ITU709 = 2,
- COLORIMETRY_EXTENDED = 3
+ COLORIMETRY_NO_DATA = 0,
+ COLORIMETRY_ITU601 = 1,
+ COLORIMETRY_ITU709 = 2,
+ COLORIMETRY_EXTENDED = 3
};
enum active_format_info {
- ACTIVE_FORMAT_NO_DATA = 0,
- ACTIVE_FORMAT_VALID = 1
+ ACTIVE_FORMAT_NO_DATA = 0, ACTIVE_FORMAT_VALID = 1
};
/* Active format aspect ratio */
enum active_format_aspect_ratio {
- ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
- ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
- ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
- ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
+ ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
+ ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
+ ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
+ ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
};
enum bar_info {
- BAR_INFO_NOT_VALID = 0,
- BAR_INFO_VERTICAL_VALID = 1,
- BAR_INFO_HORIZONTAL_VALID = 2,
- BAR_INFO_BOTH_VALID = 3
+ BAR_INFO_NOT_VALID = 0,
+ BAR_INFO_VERTICAL_VALID = 1,
+ BAR_INFO_HORIZONTAL_VALID = 2,
+ BAR_INFO_BOTH_VALID = 3
};
enum picture_scaling {
- PICTURE_SCALING_UNIFORM = 0,
- PICTURE_SCALING_HORIZONTAL = 1,
- PICTURE_SCALING_VERTICAL = 2,
- PICTURE_SCALING_BOTH = 3
+ PICTURE_SCALING_UNIFORM = 0,
+ PICTURE_SCALING_HORIZONTAL = 1,
+ PICTURE_SCALING_VERTICAL = 2,
+ PICTURE_SCALING_BOTH = 3
};
/* RGB quantization range */
enum rgb_quantization_range {
- RGB_QUANTIZATION_DEFAULT_RANGE = 0,
- RGB_QUANTIZATION_LIMITED_RANGE = 1,
- RGB_QUANTIZATION_FULL_RANGE = 2,
- RGB_QUANTIZATION_RESERVED = 3
+ RGB_QUANTIZATION_DEFAULT_RANGE = 0,
+ RGB_QUANTIZATION_LIMITED_RANGE = 1,
+ RGB_QUANTIZATION_FULL_RANGE = 2,
+ RGB_QUANTIZATION_RESERVED = 3
};
/* YYC quantization range */
enum yyc_quantization_range {
- YYC_QUANTIZATION_LIMITED_RANGE = 0,
- YYC_QUANTIZATION_FULL_RANGE = 1,
- YYC_QUANTIZATION_RESERVED2 = 2,
- YYC_QUANTIZATION_RESERVED3 = 3
+ YYC_QUANTIZATION_LIMITED_RANGE = 0,
+ YYC_QUANTIZATION_FULL_RANGE = 1,
+ YYC_QUANTIZATION_RESERVED2 = 2,
+ YYC_QUANTIZATION_RESERVED3 = 3
};
enum graphics_gamut_adjust_type {
GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
- GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */
+ GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */
};
#define CSC_TEMPERATURE_MATRIX_SIZE 9
@@ -165,36 +164,33 @@ struct scaler_data {
};
struct transform_funcs {
- void (*transform_reset)(
- struct transform *xfm);
+ void (*transform_reset)(struct transform *xfm);
- bool (*transform_power_up)(
- struct transform *xfm);
+ bool (*transform_power_up)(struct transform *xfm);
- void (*transform_set_scaler)(
- struct transform *xfm,
- const struct scaler_data *scl_data);
+ void (*transform_set_scaler)(struct transform *xfm,
+ const struct scaler_data *scl_data);
void (*transform_set_gamut_remap)(
- struct transform *xfm,
- const struct xfm_grph_csc_adjustment *adjust);
+ struct transform *xfm,
+ const struct xfm_grph_csc_adjustment *adjust);
- bool (*transform_set_pixel_storage_depth)(
- struct transform *xfm,
- enum lb_pixel_depth depth,
- const struct bit_depth_reduction_params *bit_depth_params);
+ void (*transform_set_pixel_storage_depth)(
+ struct transform *xfm,
+ enum lb_pixel_depth depth,
+ const struct bit_depth_reduction_params *bit_depth_params);
bool (*transform_get_optimal_number_of_taps)(
- struct transform *xfm,
- struct scaler_data *scl_data,
- const struct scaling_taps *in_taps);
+ struct transform *xfm,
+ struct scaler_data *scl_data,
+ const struct scaling_taps *in_taps);
};
bool transform_get_optimal_number_of_taps_helper(
- struct transform *xfm,
- struct scaler_data *scl_data,
- uint32_t pixel_width,
- const struct scaling_taps *in_taps);
+ struct transform *xfm,
+ struct scaler_data *scl_data,
+ uint32_t pixel_width,
+ const struct scaling_taps *in_taps);
extern const uint16_t filter_2tap_16p[18];
extern const uint16_t filter_2tap_64p[66];
--
2.10.1
