Make it clearer what we are doing.
Reviewed-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index fbe74a3..c5cce04 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -418,6 +418,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
u32 rb_cntl, ib_cntl;
u32 rb_bufsz;
u32 wb_offset;
+ u64 gpu_addr;
int i, j, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -464,8 +465,10 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
- WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
- WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
+ gpu_addr = ring->gpu_addr;
+ gpu_addr >>= 8;
+ WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], lower_32_bits(gpu_addr));
+ WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], upper_32_bits(gpu_addr));
ring->wptr = 0;
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
--
2.5.5
