From: Yongqiang Sun <yongqiang.sun@xxxxxxx>
Signed-off-by: Yongqiang Sun <yongqiang.sun at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/dal/dc/Makefile | 2 +-
drivers/gpu/drm/amd/dal/dc/basics/logger.c | 6 +-
drivers/gpu/drm/amd/dal/dc/core/dc.c | 6 +
drivers/gpu/drm/amd/dal/dc/core/dc_debug.c | 270 +++++++++++++++++++++
drivers/gpu/drm/amd/dal/dc/dc.h | 3 +
drivers/gpu/drm/amd/dal/include/logger_interface.h | 18 ++
drivers/gpu/drm/amd/dal/include/logger_types.h | 1 +
7 files changed, 303 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
index 834bb1814be5..f9c5db6f6cd1 100644
--- a/drivers/gpu/drm/amd/dal/dc/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
@@ -15,7 +15,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS))
include $(AMD_DC)
DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_target.o dc_sink.o dc_stream.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o
AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
index 3c16fe1d91ff..a5625a3badab 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
@@ -57,7 +57,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_EVENT_DETECTION, "Detect"},
{LOG_EVENT_LINK_TRAINING, "LKTN"},
{LOG_EVENT_LINK_LOSS, "LinkLoss"},
- {LOG_EVENT_UNDERFLOW, "Underflow"}
+ {LOG_EVENT_UNDERFLOW, "Underflow"},
+ {LOG_IF_TRACE, "InterfaceTrace"}
};
@@ -83,7 +84,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
(1 << LOG_DETECTION_EDID_PARSER) | \
(1 << LOG_DETECTION_DP_CAPS) | \
(1 << LOG_BACKLIGHT)) | \
- (1 << LOG_I2C_AUX)/* | \
+ (1 << LOG_I2C_AUX) | \
+ (1 << LOG_IF_TRACE) /* | \
(1 << LOG_SURFACE) | \
(1 << LOG_SCALER) | \
(1 << LOG_DML) | \
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index e58b27fc3322..d928b3f93ab6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1119,6 +1119,8 @@ bool dc_pre_update_surfaces_to_target(
struct validate_context *temp_context;
bool ret = true;
+ pre_surface_trace(dc, new_surfaces, new_surface_count);
+
if (core_dc->current_context->target_count == 0)
return false;
@@ -1249,6 +1251,8 @@ bool dc_post_update_surfaces_to_target(struct dc *dc)
struct core_dc *core_dc = DC_TO_CORE(dc);
int i;
+ post_surface_trace(dc);
+
for (i = 0; i < core_dc->current_context->res_ctx.pool->pipe_count; i++)
if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == NULL)
core_dc->hwss.power_down_front_end(
@@ -1320,6 +1324,8 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
int i, j;
bool is_new_pipe_surface[MAX_SURFACES];
+ update_surface_trace(dc, updates, surface_count);
+
for (j = 0; j < MAX_SURFACES; j++)
is_new_pipe_surface[j] = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_debug.c b/drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
new file mode 100644
index 000000000000..8ca0f1e0369a
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
@@ -0,0 +1,270 @@
+/*
+ * dc_debug.c
+ *
+ * Created on: Nov 3, 2016
+ * Author: yonsun
+ */
+
+#include "dm_services.h"
+
+#include "dc.h"
+
+#include "core_status.h"
+#include "core_types.h"
+#include "hw_sequencer.h"
+
+#include "resource.h"
+
+#define SURFACE_TRACE(...) do {\
+ if (dc->debug.surface_trace) \
+ dm_logger_write(logger, \
+ LOG_IF_TRACE, \
+ ##__VA_ARGS__); \
+} while (0)
+
+void pre_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface *const *surfaces,
+ int surface_count)
+{
+ int i;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct dal_logger *logger = core_dc->ctx->logger;
+
+ for (i = 0; i < surface_count; i++) {
+ const struct dc_surface *surface = surfaces[i];
+
+ SURFACE_TRACE("Surface %d:\n", i);
+
+ SURFACE_TRACE(
+ "surface->visible = %d;\n"
+ "surface->flip_immediate = %d;\n"
+ "surface->address.type = %d;\n"
+ "surface->address.grph.addr.quad_part = 0x%X;\n"
+ "surface->address.grph.meta_addr.quad_part = 0x%X;\n"
+ "surface->scaling_quality.h_taps = %d;\n"
+ "surface->scaling_quality.v_taps = %d;\n"
+ "surface->scaling_quality.h_taps_c = %d;\n"
+ "surface->scaling_quality.v_taps_c = %d;\n",
+ surface->visible,
+ surface->flip_immediate,
+ surface->address.type,
+ surface->address.grph.addr.quad_part,
+ surface->address.grph.meta_addr.quad_part,
+ surface->scaling_quality.h_taps,
+ surface->scaling_quality.v_taps,
+ surface->scaling_quality.h_taps_c,
+ surface->scaling_quality.v_taps_c);
+
+ SURFACE_TRACE(
+ "surface->src_rect.x = %d;\n"
+ "surface->src_rect.y = %d;\n"
+ "surface->src_rect.width = %d;\n"
+ "surface->src_rect.height = %d;\n"
+ "surface->dst_rect.x = %d;\n"
+ "surface->dst_rect.y = %d;\n"
+ "surface->dst_rect.width = %d;\n"
+ "surface->dst_rect.height = %d;\n"
+ "surface->clip_rect.x = %d;\n"
+ "surface->clip_rect.y = %d;\n"
+ "surface->clip_rect.width = %d;\n"
+ "surface->clip_rect.height = %d;\n",
+ surface->src_rect.x,
+ surface->src_rect.y,
+ surface->src_rect.width,
+ surface->src_rect.height,
+ surface->dst_rect.x,
+ surface->dst_rect.y,
+ surface->dst_rect.width,
+ surface->dst_rect.height,
+ surface->clip_rect.x,
+ surface->clip_rect.y,
+ surface->clip_rect.width,
+ surface->clip_rect.height);
+
+ SURFACE_TRACE(
+ "surface->plane_size.grph.surface_size.x = %d;\n"
+ "surface->plane_size.grph.surface_size.y = %d;\n"
+ "surface->plane_size.grph.surface_size.width = %d;\n"
+ "surface->plane_size.grph.surface_size.height = %d;\n"
+ "surface->plane_size.grph.surface_pitch = %d;\n"
+ "surface->plane_size.grph.meta_pitch = %d;\n",
+ surface->plane_size.grph.surface_size.x,
+ surface->plane_size.grph.surface_size.y,
+ surface->plane_size.grph.surface_size.width,
+ surface->plane_size.grph.surface_size.height,
+ surface->plane_size.grph.surface_pitch,
+ surface->plane_size.grph.meta_pitch);
+
+
+ SURFACE_TRACE(
+ "surface->tiling_info.gfx8.num_banks = %d;\n"
+ "surface->tiling_info.gfx8.bank_width = %d;\n"
+ "surface->tiling_info.gfx8.bank_width_c = %d;\n"
+ "surface->tiling_info.gfx8.bank_height = %d;\n"
+ "surface->tiling_info.gfx8.bank_height_c = %d;\n"
+ "surface->tiling_info.gfx8.tile_aspect = %d;\n"
+ "surface->tiling_info.gfx8.tile_aspect_c = %d;\n"
+ "surface->tiling_info.gfx8.tile_split = %d;\n"
+ "surface->tiling_info.gfx8.tile_split_c = %d;\n"
+ "surface->tiling_info.gfx8.tile_mode = %d;\n"
+ "surface->tiling_info.gfx8.tile_mode_c = %d;\n",
+ surface->tiling_info.gfx8.num_banks,
+ surface->tiling_info.gfx8.bank_width,
+ surface->tiling_info.gfx8.bank_width_c,
+ surface->tiling_info.gfx8.bank_height,
+ surface->tiling_info.gfx8.bank_height_c,
+ surface->tiling_info.gfx8.tile_aspect,
+ surface->tiling_info.gfx8.tile_aspect_c,
+ surface->tiling_info.gfx8.tile_split,
+ surface->tiling_info.gfx8.tile_split_c,
+ surface->tiling_info.gfx8.tile_mode,
+ surface->tiling_info.gfx8.tile_mode_c);
+
+ SURFACE_TRACE(
+ "surface->tiling_info.gfx8.pipe_config = %d;\n"
+ "surface->tiling_info.gfx8.array_mode = %d;\n"
+ "surface->color_space = %d;\n"
+ "surface->dcc.enable = %d;\n"
+ "surface->format = %d;\n"
+ "surface->rotation = %d;\n"
+ "surface->stereo_format = %d;\n",
+ surface->tiling_info.gfx8.pipe_config,
+ surface->tiling_info.gfx8.array_mode,
+ surface->color_space,
+ surface->dcc.enable,
+ surface->format,
+ surface->rotation,
+ surface->stereo_format);
+ SURFACE_TRACE("\n");
+ }
+ SURFACE_TRACE("\n");
+}
+
+void update_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface_update *updates,
+ int surface_count)
+{
+ int i;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct dal_logger *logger = core_dc->ctx->logger;
+
+ for (i = 0; i < surface_count; i++) {
+ const struct dc_surface_update *update = &updates[i];
+
+ SURFACE_TRACE("Update %d\n", i);
+ if (update->flip_addr) {
+ SURFACE_TRACE("flip_addr->address.type = %d;\n"
+ "flip_addr->address.grph.addr.quad_part = 0x%X;\n"
+ "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
+ "flip_addr->flip_immediate = %d;\n",
+ update->flip_addr->address.type,
+ update->flip_addr->address.grph.addr.quad_part,
+ update->flip_addr->address.grph.meta_addr.quad_part,
+ update->flip_addr->flip_immediate);
+ }
+
+ if (update->plane_info) {
+ SURFACE_TRACE(
+ "plane_info->color_space = %d;\n"
+ "plane_info->format = %d;\n"
+ "plane_info->plane_size.grph.meta_pitch = %d;\n"
+ "plane_info->plane_size.grph.surface_pitch = %d;\n"
+ "plane_info->plane_size.grph.surface_size.height = %d;\n"
+ "plane_info->plane_size.grph.surface_size.width = %d;\n"
+ "plane_info->plane_size.grph.surface_size.x = %d;\n"
+ "plane_info->plane_size.grph.surface_size.y = %d;\n"
+ "plane_info->rotation = %d;\n",
+ update->plane_info->color_space,
+ update->plane_info->format,
+ update->plane_info->plane_size.grph.meta_pitch,
+ update->plane_info->plane_size.grph.surface_pitch,
+ update->plane_info->plane_size.grph.surface_size.height,
+ update->plane_info->plane_size.grph.surface_size.width,
+ update->plane_info->plane_size.grph.surface_size.x,
+ update->plane_info->plane_size.grph.surface_size.y,
+ update->plane_info->rotation,
+ update->plane_info->stereo_format);
+
+ SURFACE_TRACE(
+ "plane_info->tiling_info.gfx8.num_banks = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_width = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_height = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_split = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
+ update->plane_info->tiling_info.gfx8.num_banks,
+ update->plane_info->tiling_info.gfx8.bank_width,
+ update->plane_info->tiling_info.gfx8.bank_width_c,
+ update->plane_info->tiling_info.gfx8.bank_height,
+ update->plane_info->tiling_info.gfx8.bank_height_c,
+ update->plane_info->tiling_info.gfx8.tile_aspect,
+ update->plane_info->tiling_info.gfx8.tile_aspect_c,
+ update->plane_info->tiling_info.gfx8.tile_split,
+ update->plane_info->tiling_info.gfx8.tile_split_c,
+ update->plane_info->tiling_info.gfx8.tile_mode,
+ update->plane_info->tiling_info.gfx8.tile_mode_c);
+
+ SURFACE_TRACE(
+ "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
+ "plane_info->tiling_info.gfx8.array_mode = %d;\n"
+ "plane_info->visible = %d;\n",
+ update->plane_info->tiling_info.gfx8.pipe_config,
+ update->plane_info->tiling_info.gfx8.array_mode,
+ update->plane_info->visible);
+ }
+
+ if (update->scaling_info) {
+ SURFACE_TRACE(
+ "scaling_info->src_rect.x = %d;\n"
+ "scaling_info->src_rect.y = %d;\n"
+ "scaling_info->src_rect.width = %d;\n"
+ "scaling_info->src_rect.height = %d;\n"
+ "scaling_info->dst_rect.x = %d;\n"
+ "scaling_info->dst_rect.y = %d;\n"
+ "scaling_info->dst_rect.width = %d;\n"
+ "scaling_info->dst_rect.height = %d;\n"
+ "scaling_info->clip_rect.x = %d;\n"
+ "scaling_info->clip_rect.y = %d;\n"
+ "scaling_info->clip_rect.width = %d;\n"
+ "scaling_info->clip_rect.height = %d;\n"
+ "scaling_info->scaling_quality.h_taps = %d;\n"
+ "scaling_info->scaling_quality.v_taps = %d;\n"
+ "scaling_info->scaling_quality.h_taps_c = %d;\n"
+ "scaling_info->scaling_quality.v_taps_c = %d;\n",
+ update->scaling_info->src_rect.x,
+ update->scaling_info->src_rect.y,
+ update->scaling_info->src_rect.width,
+ update->scaling_info->src_rect.height,
+ update->scaling_info->dst_rect.x,
+ update->scaling_info->dst_rect.y,
+ update->scaling_info->dst_rect.width,
+ update->scaling_info->dst_rect.height,
+ update->scaling_info->clip_rect.x,
+ update->scaling_info->clip_rect.y,
+ update->scaling_info->clip_rect.width,
+ update->scaling_info->clip_rect.height,
+ update->scaling_info->scaling_quality.h_taps,
+ update->scaling_info->scaling_quality.v_taps,
+ update->scaling_info->scaling_quality.h_taps_c,
+ update->scaling_info->scaling_quality.v_taps_c);
+ }
+ SURFACE_TRACE("\n");
+ }
+ SURFACE_TRACE("\n");
+}
+
+void post_surface_trace(const struct dc *dc)
+{
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct dal_logger *logger = core_dc->ctx->logger;
+
+ SURFACE_TRACE("post surface process.\n");
+
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index d73ae63b4ec9..26624e2661fa 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -141,6 +141,9 @@ struct dc_debug {
bool disable_dcc;
bool disable_dfs_bypass;
bool max_disp_clk;
+ bool target_trace;
+ bool surface_trace;
+ bool validation_trace;
};
struct dc {
diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h
index 859215630914..b58d30de8293 100644
--- a/drivers/gpu/drm/amd/dal/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h
@@ -30,6 +30,7 @@
struct dc_context;
struct dc_link;
+struct dc_surface_update;
/*
*
@@ -67,6 +68,23 @@ void dc_conn_log(struct dc_context *ctx,
const char *msg,
...);
+void logger_write(struct dal_logger *logger,
+ enum dc_log_type log_type,
+ const char *msg,
+ void *paralist);
+
+void pre_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface *const *surfaces,
+ int surface_count);
+
+void update_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface_update *updates,
+ int surface_count);
+
+void post_surface_trace(const struct dc *dc);
+
/* Any function which is empty or have incomplete implementation should be
* marked by this macro.
diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
index 1ea60bb9e716..babd6523b105 100644
--- a/drivers/gpu/drm/amd/dal/include/logger_types.h
+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
@@ -61,6 +61,7 @@ enum dc_log_type {
LOG_EVENT_LINK_TRAINING,
LOG_EVENT_LINK_LOSS,
LOG_EVENT_UNDERFLOW,
+ LOG_IF_TRACE,
LOG_SECTION_TOTAL_COUNT
};
--
2.10.1
