From: Tony Cheng <tony.cheng@xxxxxxx>
- move blnd programming to new method
- separate out DCE11 underlay support.
- fix stoney wrong offsets
Signed-off-by: Tony Cheng <tony.cheng at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 6 +-
drivers/gpu/drm/amd/dal/dc/dc_helper.c | 16 +++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 81 +++++++++++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 98 ++++++++++++--
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 114 ----------------
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 150 +--------------------
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 35 ++++-
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 126 -----------------
.../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 94 +------------
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 13 +-
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 27 +++-
11 files changed, 252 insertions(+), 508 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 9c8550bc8c06..7636fc6d7052 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1446,7 +1446,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
if (updates[i].flip_addr) {
core_dc->hwss.pipe_control_lock(
- core_dc->ctx,
+ core_dc->hwseq,
pipe_ctx->pipe_idx,
PIPE_LOCK_CONTROL_SURFACE,
true);
@@ -1460,7 +1460,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
- core_dc->ctx,
+ core_dc->hwseq,
pipe_ctx->pipe_idx,
PIPE_LOCK_CONTROL_SURFACE |
PIPE_LOCK_CONTROL_GRAPHICS |
@@ -1486,7 +1486,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
if (updates[j].surface == &pipe_ctx->surface->public) {
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
- core_dc->ctx,
+ core_dc->hwseq,
pipe_ctx->pipe_idx,
PIPE_LOCK_CONTROL_GRAPHICS |
PIPE_LOCK_CONTROL_SCL |
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helper.c b/drivers/gpu/drm/amd/dal/dc/dc_helper.c
index 6ac801422c63..b3f7d40673e8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/dal/dc/dc_helper.c
@@ -61,6 +61,22 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
return reg_val;
}
+uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
+{
+ uint32_t reg_val = dm_read_reg(ctx, addr);
+ *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
+ *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
+ *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
+ *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
+ *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
+ return reg_val;
+}
+
/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
* compiler won't be able to check for size match and is prone to stack corruption type of bugs
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
index 2eab8fb3be7d..80f827ba63b4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -25,6 +25,7 @@
#include "dce_hwseq.h"
#include "reg_helper.h"
+#include "hw_sequencer.h"
#define CTX \
hws->ctx
@@ -41,3 +42,83 @@ void dce_enable_fe_clock(struct dce_hwseq *hws,
REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
DCFE_CLOCK_ENABLE, enable);
}
+
+void dce_pipe_control_lock(struct dce_hwseq *hws,
+ unsigned int blnd_inst,
+ enum pipe_lock_control control_mask,
+ bool lock)
+{
+ uint32_t lock_val = lock ? 1 : 0;
+ uint32_t dcp_grph, scl, dcp_grph_surf, blnd, update_lock_mode;
+
+ uint32_t val = REG_GET_5(BLND_V_UPDATE_LOCK[blnd_inst],
+ BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
+ BLND_SCL_V_UPDATE_LOCK, &scl,
+ BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf,
+ BLND_BLND_V_UPDATE_LOCK, &blnd,
+ BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
+
+ if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
+ dcp_grph = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_SCL)
+ scl = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
+ dcp_grph_surf = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_BLENDER)
+ blnd = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_MODE)
+ update_lock_mode = lock_val;
+
+ REG_SET_5(BLND_V_UPDATE_LOCK[blnd_inst], val,
+ BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
+ BLND_SCL_V_UPDATE_LOCK, &scl,
+ BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf,
+ BLND_BLND_V_UPDATE_LOCK, &blnd,
+ BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
+
+ if (hws->wa.blnd_crtc_trigger)
+ if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {
+ uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]);
+ REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value);
+ }
+}
+
+void dce_set_blender_mode(struct dce_hwseq *hws,
+ unsigned int blnd_inst,
+ enum blnd_mode mode)
+{
+ uint32_t feedthrough = 1;
+ uint32_t blnd_mode = 0;
+ uint32_t multiplied_mode = 0;
+ uint32_t alpha_mode = 2;
+
+ switch (mode) {
+ case BLND_MODE_OTHER_PIPE:
+ feedthrough = 0;
+ blnd_mode = 1;
+ alpha_mode = 0;
+ break;
+ case BLND_MODE_BLENDING:
+ feedthrough = 0;
+ blnd_mode = 2;
+ alpha_mode = 0;
+ multiplied_mode = 1;
+ break;
+ case BLND_MODE_CURRENT_PIPE:
+ default:
+ if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
+ blnd_inst == 0)
+ feedthrough = 0;
+ break;
+ }
+
+ REG_UPDATE_4(BLND_CONTROL[blnd_inst],
+ BLND_FEEDTHROUGH_EN, feedthrough,
+ BLND_ALPHA_MODE, alpha_mode,
+ BLND_MODE, blnd_mode,
+ BLND_MULTIPLIED_MODE, multiplied_mode);
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
index b12b2a3b1405..11bff8750999 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -27,42 +27,102 @@
#include "hw_sequencer.h"
-#define HWSEQ_DCE8_REG_LIST_BASE() \
+#define HWSEQ_DCEF_REG_LIST_DCE8() \
.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
- .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
-#define HWSEQ_COMMON_REG_LIST_BASE() \
+#define HWSEQ_DCEF_REG_LIST() \
SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
- SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 5)
+
+#define HWSEQ_BLND_REG_LIST() \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
+ SRII(BLND_CONTROL, BLND, 0), \
+ SRII(BLND_CONTROL, BLND, 1), \
+ SRII(BLND_CONTROL, BLND, 2), \
+ SRII(BLND_CONTROL, BLND, 3), \
+ SRII(BLND_CONTROL, BLND, 4), \
+ SRII(BLND_CONTROL, BLND, 5)
+
+#define HWSEQ_DCE8_REG_LIST_BASE() \
+ HWSEQ_DCEF_REG_LIST_DCE8(), \
+ HWSEQ_BLND_REG_LIST(), \
+#define HWSEQ_COMMON_REG_LIST_BASE() \
+ HWSEQ_DCEF_REG_LIST(), \
+ HWSEQ_BLND_REG_LIST()
+
+struct dce_hwseq_registers {
+ uint32_t DCFE_CLOCK_CONTROL[6];
+ uint32_t BLND_V_UPDATE_LOCK[6];
+ uint32_t BLND_CONTROL[6];
+ uint32_t BLNDV_CONTROL;
+ uint32_t CRTC_H_BLANK_START_END[6];
+};
/* set field name */
-#define SF(reg_name, field_name, post_fix)\
- .field_name = reg_name ## __ ## field_name ## post_fix
+#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
+ .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
+
+#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
+ HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh)
+
+#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
#define HWSEQ_DCE8_MASK_SH_LIST_BASE(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
+ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh)
#define HWSEQ_COMMON_MASK_SH_LIST_BASE(mask_sh)\
- SF(DCFE_CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
+ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
+ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_)
-struct dce_hwseq_registers {
- uint32_t DCFE_CLOCK_CONTROL[6];
-};
+#define HWSEQ_REG_FIED_LIST(type) \
+ type DCFE_CLOCK_ENABLE; \
+ type BLND_DCP_GRPH_V_UPDATE_LOCK; \
+ type BLND_SCL_V_UPDATE_LOCK; \
+ type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
+ type BLND_BLND_V_UPDATE_LOCK; \
+ type BLND_V_UPDATE_LOCK_MODE; \
+ type BLND_FEEDTHROUGH_EN; \
+ type BLND_ALPHA_MODE; \
+ type BLND_MODE; \
+ type BLND_MULTIPLIED_MODE; \
struct dce_hwseq_shift {
- uint8_t DCFE_CLOCK_ENABLE;
+ HWSEQ_REG_FIED_LIST(uint8_t)
};
struct dce_hwseq_mask {
- uint32_t DCFE_CLOCK_ENABLE;
+ HWSEQ_REG_FIED_LIST(uint32_t)
+};
+
+struct dce_hwseq_wa {
+ bool blnd_crtc_trigger;
};
struct dce_hwseq {
@@ -70,9 +130,23 @@ struct dce_hwseq {
const struct dce_hwseq_registers *regs;
const struct dce_hwseq_shift *shifts;
const struct dce_hwseq_mask *masks;
+ struct dce_hwseq_wa wa;
};
void dce_enable_fe_clock(struct dce_hwseq *hwss,
unsigned int inst, bool enable);
+void dce_pipe_control_lock(struct dce_hwseq *hws,
+ unsigned int blnd_inst,
+ enum pipe_lock_control control_mask,
+ bool lock);
+
+enum blnd_mode {
+ BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ BLND_MODE_STEREO
+};
+void dce_set_blender_mode(struct dce_hwseq *hws,
+ unsigned int blnd_inst, enum blnd_mode mode);
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index b17cdf702fec..a7fa7ede2ec2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -39,43 +39,27 @@ struct dce100_hw_seq_reg_offsets {
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
-
static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-#define HW_REG_BLND(reg, id)\
- (reg + reg_offsets[id].blnd)
-
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
@@ -84,102 +68,6 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static bool dce100_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_BLND_V_UPDATE_LOCK);
- }
-
- if (control_mask & PIPE_LOCK_CONTROL_MODE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_V_UPDATE_LOCK_MODE);
-
- dm_write_reg(ctx, addr, value);
-
-
- return true;
-}
-
-static void dce100_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t blnd_mode;
- uint32_t feedthrough = 0;
-
- struct dc_context *ctx = dc->ctx;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- blnd_mode = 2;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- feedthrough = 1;
- blnd_mode = 0;
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- feedthrough,
- BLND_CONTROL,
- BLND_FEEDTHROUGH_EN);
-
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static bool dce100_enable_display_power_gating(
struct core_dc *dc,
uint8_t controller_id,
@@ -269,8 +157,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce100_power_up;
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
- dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
- dc->hwss.set_blender_mode = dce100_set_blender_mode;
dc->hwss.set_displaymarks = set_displaymarks;
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
dc->hwss.set_bandwidth = set_bandwidth;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index c4a2bbf57dcd..10b55e77ecc0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -53,32 +53,20 @@
#include "dce/dce_11_0_sh_mask.h"
struct dce110_hw_seq_reg_offsets {
- uint32_t blnd;
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
-
static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLNDV_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
@@ -163,132 +151,6 @@ static void dce110_init_pte(struct dc_context *ctx)
}
}
-/* this is a workaround for hw bug - it is a trigger on r/w */
-static void trigger_write_crtc_h_blank_start_end(
- struct dc_context *ctx,
- uint8_t controller_id)
-{
- uint32_t value;
- uint32_t addr;
-
- addr = HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id);
- value = dm_read_reg(ctx, addr);
- dm_write_reg(ctx, addr, value);
-}
-
-static bool dce110_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_BLND_V_UPDATE_LOCK);
- }
-
- if (control_mask & PIPE_LOCK_CONTROL_MODE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_V_UPDATE_LOCK_MODE);
-
- dm_write_reg(ctx, addr, value);
-
- if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER))
- trigger_write_crtc_h_blank_start_end(ctx, controller_idx);
-
- return true;
-}
-
-static void dce110_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t alpha_mode = 2;
- uint32_t blnd_mode = 0;
- uint32_t feedthrough = 1;
- uint32_t multiplied_mode = 0;
-
- struct dc_context *ctx = dc->ctx;
- unsigned int underlay_idx = dc->current_context->res_ctx.pool->underlay_pipe_index;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 2;
- multiplied_mode = 1;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- if (controller_id == underlay_idx || controller_id == 0)
- feedthrough = 0;
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- feedthrough,
- BLND_CONTROL,
- BLND_FEEDTHROUGH_EN);
- set_reg_field_value(
- value,
- alpha_mode,
- BLND_CONTROL,
- BLND_ALPHA_MODE);
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
- set_reg_field_value(
- value,
- multiplied_mode,
- BLND_CONTROL,
- BLND_MULTIPLIED_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static void dce110_crtc_switch_to_clk_src(
struct clock_source *clk_src, uint8_t crtc_inst)
{
@@ -1557,18 +1419,17 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
static void program_blender(const struct core_dc *dc,
struct pipe_ctx *pipe_ctx)
{
- enum blender_mode blender_mode = BLENDER_MODE_CURRENT_PIPE;
+ enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
if (pipe_ctx->bottom_pipe) {
if (pipe_ctx->bottom_pipe->surface->public.visible) {
if (pipe_ctx->surface->public.visible)
- blender_mode = BLENDER_MODE_BLENDING;
+ blender_mode = BLND_MODE_BLENDING;
else
- blender_mode = BLENDER_MODE_OTHER_PIPE;
+ blender_mode = BLND_MODE_OTHER_PIPE;
}
}
- dc->hwss.set_blender_mode(
- (struct core_dc *)dc, pipe_ctx->pipe_idx, blender_mode);
+ dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
}
/**
@@ -2134,8 +1995,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
- .pipe_control_lock = dce110_pipe_control_lock,
- .set_blender_mode = dce110_set_blender_mode,
+ .pipe_control_lock = dce_pipe_control_lock,
.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
.set_display_clock = dce110_set_display_clock,
.set_displaymarks = dce110_set_displaymarks,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index e0e3178b9134..e19a69419c5c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -425,16 +425,39 @@ static struct stream_encoder *dce110_stream_encoder_create(
#define SRII(reg_name, block, id)\
.reg_name[id] = mm ## block ## id ## _ ## reg_name
-static const struct dce_hwseq_registers hwseq_reg = {
- HWSEQ_COMMON_REG_LIST_BASE()
+#define HWSEQ_DCE11_REG_LIST_BASE() \
+ HWSEQ_DCEF_REG_LIST(),\
+ SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
+ SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
+ SRII(BLND_CONTROL, BLND, 0),\
+ SRII(BLND_CONTROL, BLND, 1),\
+ .BLNDV_CONTROL = mmBLNDV_CONTROL
+
+static const struct dce_hwseq_registers hwseq_stoney_reg = {
+ HWSEQ_DCE11_REG_LIST_BASE(),
+ .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END,
+ .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK,
+ .BLND_CONTROL[2] = mmBLNDV_CONTROL,
+};
+
+static const struct dce_hwseq_registers hwseq_cz_reg = {
+ HWSEQ_DCE11_REG_LIST_BASE(),
+ SRII(CRTC_H_BLANK_START_END, CRTC, 2),
+ SRII(BLND_V_UPDATE_LOCK, BLND, 2),
+ SRII(BLND_CONTROL, BLND, 2),
+ .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END,
+ .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK,
+ .BLND_CONTROL[3] = mmBLNDV_CONTROL,
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT),
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK),
};
static struct dce_hwseq *dce110_hwseq_create(
@@ -444,9 +467,11 @@ static struct dce_hwseq *dce110_hwseq_create(
if (hws) {
hws->ctx = ctx;
- hws->regs = &hwseq_reg;
+ hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
+ &hwseq_stoney_reg : &hwseq_cz_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
+ hws->wa.blnd_crtc_trigger = true;
}
return hws;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index f8c2cfb64b11..4021b0b1e3a9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -29,7 +29,6 @@
#include "core_types.h"
#include "dce112_hw_sequencer.h"
-#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
#include "gpu/dce112/dc_clock_gating_dce112.h"
@@ -38,47 +37,30 @@
#include "dce/dce_11_2_sh_mask.h"
struct dce112_hw_seq_reg_offsets {
- uint32_t blnd;
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-
-#define HW_REG_BLND(reg, id)\
- (reg + reg_offsets[id].blnd)
-
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
@@ -87,112 +69,6 @@ static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static bool dce112_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_BLND_V_UPDATE_LOCK);
- }
-
- if (control_mask & PIPE_LOCK_CONTROL_MODE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_V_UPDATE_LOCK_MODE);
-
- dm_write_reg(ctx, addr, value);
-
- return true;
-}
-
-static void dce112_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t alpha_mode = 2;
- uint32_t blnd_mode = 0;
- uint32_t feedthrough = 1;
- uint32_t multiplied_mode = 0;
- struct dc_context *ctx = dc->ctx;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 2;
- multiplied_mode = 1;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- feedthrough,
- BLND_CONTROL,
- BLND_FEEDTHROUGH_EN);
- set_reg_field_value(
- value,
- alpha_mode,
- BLND_CONTROL,
- BLND_ALPHA_MODE);
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
- set_reg_field_value(
- value,
- multiplied_mode,
- BLND_CONTROL,
- BLND_MULTIPLIED_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static void dce112_crtc_switch_to_clk_src(
struct clock_source *clk_src, uint8_t crtc_inst)
{
@@ -321,8 +197,6 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
- dc->hwss.pipe_control_lock = dce112_pipe_control_lock;
- dc->hwss.set_blender_mode = dce112_set_blender_mode;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
index d52513ba46a8..a69e609b9e75 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
@@ -39,47 +39,30 @@
#include "dce/dce_8_0_sh_mask.h"
struct dce80_hw_seq_reg_offsets {
- uint32_t blnd;
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
-
static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-#define HW_REG_BLND(reg, id)\
- (reg + reg_offsets[id].blnd)
-
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
@@ -89,80 +72,6 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
/***************************PIPE_CONTROL***********************************/
-static bool dce80_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- dm_write_reg(ctx, addr, value);
-
- return true;
-}
-
-static void dce80_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t blnd_mode;
- uint32_t feedthrough = 0;
-
- struct dc_context *ctx = dc->ctx;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- blnd_mode = 2;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- feedthrough = 1;
- blnd_mode = 0;
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static bool dce80_enable_display_power_gating(
struct core_dc *dc,
uint8_t controller_id,
@@ -225,8 +134,7 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce80_power_up;
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
- dc->hwss.pipe_control_lock = dce80_pipe_control_lock;
- dc->hwss.set_blender_mode = dce80_set_blender_mode;
+ dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc->hwss.set_displaymarks = set_displaymarks;
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
dc->hwss.set_bandwidth = set_bandwidth;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index 7091dc731d09..dcaac8a336d1 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -121,17 +121,12 @@ struct hw_sequencer_funcs {
void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings);
- bool (*pipe_control_lock)(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
+ void (*pipe_control_lock)(
+ struct dce_hwseq *hwseq,
+ unsigned int blnd_inst,
+ enum pipe_lock_control control_mask,
bool lock);
- void (*set_blender_mode)(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode);
-
void (*set_displaymarks)(
const struct core_dc *dc,
struct validate_context *context);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
index 4c1286dc3bdb..f0cf64b1d54e 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
@@ -80,6 +80,15 @@
FN(reg, f3), v3,\
FN(reg, f4), v4)
+#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
+ f5, v5) \
+ REG_SET_N(reg, 6, init_value, \
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4,\
+ FN(reg, f5), v5)
+
#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
f5, v5, f6, v6) \
REG_SET_N(reg, 6, init_value, \
@@ -101,7 +110,8 @@
FN(reg, f6), v6,\
FN(reg, f7), v7)
-#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
+#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
+ v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
REG_SET_N(reg, 10, init_value, \
FN(reg, f1), v1,\
FN(reg, f2), v2, \
@@ -131,6 +141,14 @@
FN(reg_name, f2), v2, \
FN(reg_name, f3), v3)
+#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ generic_reg_get5(CTX, REG(reg_name), \
+ FN(reg_name, f1), v1, \
+ FN(reg_name, f2), v2, \
+ FN(reg_name, f3), v3, \
+ FN(reg_name, f4), v4, \
+ FN(reg_name, f5), v5)
+
/* macro to poll and wait for a register field to read back given value */
#define REG_WAIT(reg_name, field, val, delay, max_try) \
@@ -260,4 +278,11 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
+uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
+
#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_REG_HELPER_H_ */
--
2.10.1
