From: Zeyu Fan <Zeyu.Fan@xxxxxxx>
Signed-off-by: Zeyu Fan <Zeyu.Fan at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 5 +-
drivers/gpu/drm/amd/dal/dc/dce/Makefile | 2 +-
.../dce_link_encoder.c} | 10 +-
.../dce_link_encoder.h} | 0
...ce110_stream_encoder.c => dce_stream_encoder.c} | 4 +-
...ce110_stream_encoder.h => dce_stream_encoder.h} | 0
drivers/gpu/drm/amd/dal/dc/dce100/Makefile | 2 +-
.../drm/amd/dal/dc/dce100/dce100_link_encoder.c | 92 ------
.../drm/amd/dal/dc/dce100/dce100_link_encoder.h | 42 ---
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 13 +-
drivers/gpu/drm/amd/dal/dc/dce110/Makefile | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 11 +-
drivers/gpu/drm/amd/dal/dc/dce112/Makefile | 2 +-
.../drm/amd/dal/dc/dce112/dce112_link_encoder.c | 191 ------------
.../drm/amd/dal/dc/dce112/dce112_link_encoder.h | 41 ---
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 14 +-
drivers/gpu/drm/amd/dal/dc/dce80/Makefile | 2 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c | 333 ---------------------
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h | 39 ---
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 14 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 1 +
21 files changed, 50 insertions(+), 770 deletions(-)
rename drivers/gpu/drm/amd/dal/dc/{dce110/dce110_link_encoder.c => dce/dce_link_encoder.c} (99%)
rename drivers/gpu/drm/amd/dal/dc/{dce110/dce110_link_encoder.h => dce/dce_link_encoder.h} (100%)
rename drivers/gpu/drm/amd/dal/dc/dce/{dce110_stream_encoder.c => dce_stream_encoder.c} (99%)
rename drivers/gpu/drm/amd/dal/dc/dce/{dce110_stream_encoder.h => dce_stream_encoder.h} (100%)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
index f01338671143..bc240981d276 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
@@ -1,5 +1,6 @@
/* Copyright 2015 Advanced Micro Devices, Inc. */
+
#include "dm_services.h"
#include "dc.h"
#include "inc/core_dc.h"
@@ -9,8 +10,8 @@
#include "hw_sequencer.h"
#include "dc_link_ddc.h"
#include "dm_helpers.h"
-#include "dce110/dce110_link_encoder.h"
-#include "dce/dce110_stream_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
enum dc_status core_link_read_dpcd(
struct core_link* link,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/Makefile b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
index 04d9a351388a..306070dd5455 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
@@ -5,7 +5,7 @@
# - register programming through common macros that look up register
# offset/shift/mask stored in dce_hw struct
-DCE = dce_audio.o dce110_stream_encoder.o
+DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
similarity index 99%
rename from drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index c36cdadf35f2..8a9060601005 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -23,12 +23,13 @@
*
*/
+
+
#include "dm_services.h"
#include "core_types.h"
#include "link_encoder.h"
+#include "dce_link_encoder.h"
#include "stream_encoder.h"
-#include "dce110_link_encoder.h"
-
#include "i2caux_interface.h"
#include "dc_bios_types.h"
@@ -907,7 +908,8 @@ static bool dce110_link_encoder_validate_hdmi_output(
return false;
/* DCE11 HW does not support 420 */
- if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ if (!enc110->base.features.ycbcr420_supported &&
+ crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
return true;
@@ -993,8 +995,6 @@ bool dce110_link_encoder_construct(
enc110->base.features.max_pixel_clock =
MAX_ENCODER_CLK;
- enc110->base.features.max_hdmi_pixel_clock =
- DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
similarity index 100%
rename from drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
similarity index 99%
rename from drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index f2f66ea49fea..079734700c15 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -23,10 +23,10 @@
*
*/
+
#include "dm_services.h"
#include "dc_bios_types.h"
-#include "dce110_stream_encoder.h"
-
+#include "dce_stream_encoder.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce/dce_11_0_enum.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
similarity index 100%
rename from drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.h
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
index 5fb7e7b702b7..656c38e1b0f5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE100 = dce100_resource.o dce100_hw_sequencer.o dce100_link_encoder.o
+DCE100 = dce100_resource.o dce100_hw_sequencer.o
AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
deleted file mode 100644
index 0e85ce2862cd..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "dce100_link_encoder.h"
-#include "stream_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-#include "i2caux_interface.h"
-
-/* TODO: change to dce80 header file */
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-#include "dce/dce_10_0_enum.h"
-
-#define LINK_REG(reg)\
- (enc110->link_regs->reg)
-
-#define DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 300000
-
-
-static const struct link_encoder_funcs dce100_lnk_enc_funcs = {
- .validate_output_with_stream =
- dce110_link_encoder_validate_output_with_stream,
- .hw_init = dce110_link_encoder_hw_init,
- .setup = dce110_link_encoder_setup,
- .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
- .enable_dp_output = dce110_link_encoder_enable_dp_output,
- .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
- .disable_output = dce110_link_encoder_disable_output,
- .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
- .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
- .update_mst_stream_allocation_table =
- dce110_link_encoder_update_mst_stream_allocation_table,
- .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- .set_dmcu_backlight_level =
- dce110_link_encoder_set_dmcu_backlight_level,
- .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level,
- .backlight_control = dce110_link_encoder_edp_backlight_control,
- .power_control = dce110_link_encoder_edp_power_control,
- .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
- .destroy = dce110_link_encoder_destroy
-};
-
-bool dce100_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs)
-{
- dce110_link_encoder_construct(
- enc110,
- init_data,
- link_regs,
- aux_regs,
- hpd_regs);
-
- enc110->base.funcs = &dce100_lnk_enc_funcs;
-
- enc110->base.features.flags.bits.IS_HBR3_CAPABLE = false;
- enc110->base.features.flags.bits.IS_TPS4_CAPABLE = false;
-
- enc110->base.features.max_hdmi_pixel_clock =
- DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
- enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
- enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
deleted file mode 100644
index af5b8648ef7d..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_LINK_ENCODER__DCE100_H__
-#define __DC_LINK_ENCODER__DCE100_H__
-
-#include "link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-
-#define TO_DCE100_LINK_ENC(link_encoder)\
- container_of(link_encoder, struct dce100_link_encoder, base)
-
-bool dce100_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs);
-
-#endif /* __DC_LINK_ENCODER__DCE100_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 42c1eff389a3..ea7e12d8a1e4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -34,13 +34,12 @@
#include "dce110/dce110_resource.h"
#include "dce110/dce110_timing_generator.h"
#include "irq/dce110/irq_service_dce110.h"
-#include "dce110/dce110_link_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_mem_input_v.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_transform.h"
-#include "dce100/dce100_link_encoder.h"
-#include "dce/dce110_stream_encoder.h"
#include "dce110/dce110_opp.h"
#include "dce110/dce110_clock_source.h"
#include "dce/dce_audio.h"
@@ -515,13 +514,17 @@ struct link_encoder *dce100_link_encoder_create(
if (!enc110)
return NULL;
- if (dce100_link_encoder_construct(
+ if (dce110_link_encoder_construct(
enc110,
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 300000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
index 5393a685e9c3..ed271240cbdf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
@@ -3,7 +3,7 @@
# It provides the control and status of HW CRTC block.
DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
-dce110_ipp_gamma.o dce110_link_encoder.o dce110_opp.o \
+dce110_ipp_gamma.o dce110_opp.o \
dce110_opp_formatter.o dce110_opp_regamma.o \
dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 6e6e2a629175..0404122cf31e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -30,18 +30,19 @@
#include "resource.h"
#include "dce110/dce110_resource.h"
+
#include "include/irq_service_interface.h"
#include "dce/dce_audio.h"
#include "dce110/dce110_timing_generator.h"
#include "irq/dce110/irq_service_dce110.h"
#include "dce110/dce110_timing_generator_v.h"
-#include "dce110/dce110_link_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_mem_input_v.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_transform.h"
#include "dce110/dce110_transform_v.h"
-#include "dce/dce110_stream_encoder.h"
#include "dce110/dce110_opp.h"
#include "dce110/dce110_opp_v.h"
#include "dce110/dce110_clock_source.h"
@@ -495,8 +496,12 @@ struct link_encoder *dce110_link_encoder_create(
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 594000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/Makefile b/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
index c6e3c8c2133a..010e10b48042 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE112 = dce112_link_encoder.o dce112_compressor.o dce112_hw_sequencer.o \
+DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
dce112_resource.o dce112_clock_source.o dce112_mem_input.o dce112_opp_formatter.o \
dce112_opp.o
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
deleted file mode 100644
index 88ed54f48755..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "link_encoder.h"
-#include "stream_encoder.h"
-#include "dce112_link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-#include "i2caux_interface.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLK 600000
-
-#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 600000
-
-#define DEFAULT_AUX_MAX_DATA_SIZE 16
-#define AUX_MAX_DEFER_WRITE_RETRY 20
-
-/* all values are in milliseconds */
-/* For eDP, after power-up/power/down,
- * 300/500 msec max. delay from LCDVCC to black video generation */
-#define PANEL_POWER_UP_TIMEOUT 300
-#define PANEL_POWER_DOWN_TIMEOUT 500
-#define HPD_CHECK_INTERVAL 10
-
-/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-#define TMDS_MIN_PIXEL_CLOCK 25000
-/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-#define TMDS_MAX_PIXEL_CLOCK 165000
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLOCK 600000
-
-enum {
- DP_MST_UPDATE_MAX_RETRY = 50
-};
-
-static void dce112_link_encoder_dp_set_phy_pattern(
- struct link_encoder *enc,
- const struct encoder_set_dp_phy_pattern_param *param)
-{
- switch (param->dp_phy_pattern) {
- case DP_TEST_PATTERN_TRAINING_PATTERN4:
- dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
- break;
- default:
- dce110_link_encoder_dp_set_phy_pattern(enc, param);
- break;
- }
-}
-
-static bool dce112_link_encoder_validate_hdmi_output(
- const struct dce110_link_encoder *enc110,
- const struct dc_crtc_timing *crtc_timing,
- int adjusted_pix_clk_khz)
-{
- enum dc_color_depth max_deep_color =
- enc110->base.features.max_hdmi_deep_color;
-
- if (max_deep_color > enc110->base.features.max_deep_color)
- max_deep_color = enc110->base.features.max_deep_color;
-
- if (max_deep_color < crtc_timing->display_color_depth)
- return false;
-
- if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
- return false;
-
- if ((adjusted_pix_clk_khz == 0) ||
- (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock) ||
- (adjusted_pix_clk_khz > enc110->base.features.max_pixel_clock))
- return false;
-
- return true;
-}
-
-bool dce112_link_encoder_validate_output_with_stream(
- struct link_encoder *enc,
- struct pipe_ctx *pipe_ctx)
-{
- struct core_stream *stream = pipe_ctx->stream;
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- bool is_valid;
-
- switch (pipe_ctx->stream->signal) {
- case SIGNAL_TYPE_DVI_SINGLE_LINK:
- case SIGNAL_TYPE_DVI_DUAL_LINK:
- is_valid = dce110_link_encoder_validate_dvi_output(
- enc110,
- stream->sink->link->public.connector_signal,
- pipe_ctx->stream->signal,
- &stream->public.timing);
- break;
- case SIGNAL_TYPE_HDMI_TYPE_A:
- is_valid = dce112_link_encoder_validate_hdmi_output(
- enc110,
- &stream->public.timing,
- stream->phy_pix_clk);
- break;
- case SIGNAL_TYPE_RGB:
- is_valid = dce110_link_encoder_validate_rgb_output(
- enc110, &stream->public.timing);
- break;
- case SIGNAL_TYPE_DISPLAY_PORT:
- case SIGNAL_TYPE_DISPLAY_PORT_MST:
- case SIGNAL_TYPE_EDP:
- is_valid = dce110_link_encoder_validate_dp_output(
- enc110, &stream->public.timing);
- break;
- case SIGNAL_TYPE_WIRELESS:
- is_valid = dce110_link_encoder_validate_wireless_output(
- enc110, &stream->public.timing);
- break;
- default:
- is_valid = true;
- break;
- }
-
- return is_valid;
-}
-
-static const struct link_encoder_funcs dce112_lnk_enc_funcs = {
- .validate_output_with_stream =
- dce112_link_encoder_validate_output_with_stream,
- .hw_init = dce110_link_encoder_hw_init,
- .setup = dce110_link_encoder_setup,
- .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
- .enable_dp_output = dce110_link_encoder_enable_dp_output,
- .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
- .disable_output = dce110_link_encoder_disable_output,
- .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
- .dp_set_phy_pattern = dce112_link_encoder_dp_set_phy_pattern,
- .update_mst_stream_allocation_table =
- dce110_link_encoder_update_mst_stream_allocation_table,
- .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- .set_dmcu_backlight_level =
- dce110_link_encoder_set_dmcu_backlight_level,
- .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level,
- .backlight_control = dce110_link_encoder_edp_backlight_control,
- .power_control = dce110_link_encoder_edp_power_control,
- .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
- .enable_hpd = dce110_link_encoder_enable_hpd,
- .disable_hpd = dce110_link_encoder_disable_hpd,
- .destroy = dce110_link_encoder_destroy
-};
-
-bool dce112_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs)
-{
- dce110_link_encoder_construct(
- enc110,
- init_data,
- link_regs,
- aux_regs,
- hpd_regs);
-
- enc110->base.funcs = &dce112_lnk_enc_funcs;
-
- enc110->base.features.flags.bits.IS_HBR3_CAPABLE = false;
-
- enc110->base.features.flags.bits.IS_TPS4_CAPABLE = false;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
deleted file mode 100644
index ab373359dd9e..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_LINK_ENCODER__DCE112_H__
-#define __DC_LINK_ENCODER__DCE112_H__
-
-#include "link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-
-bool dce112_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs);
-
-/****************** HW programming ************************/
-
-#endif /* __DC_LINK_ENCODER__DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 485221696c26..8588a94e0fc5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -34,11 +34,11 @@
#include "dce110/dce110_resource.h"
#include "dce110/dce110_timing_generator.h"
#include "dce112/dce112_mem_input.h"
-#include "dce112/dce112_link_encoder.h"
-#include "dce110/dce110_link_encoder.h"
+
#include "irq/dce110/irq_service_dce110.h"
#include "dce110/dce110_transform.h"
-#include "dce/dce110_stream_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce/dce_audio.h"
#include "dce112/dce112_opp.h"
#include "dce110/dce110_ipp.h"
@@ -518,13 +518,17 @@ struct link_encoder *dce112_link_encoder_create(
if (!enc110)
return NULL;
- if (dce112_link_encoder_construct(
+ if (dce110_link_encoder_construct(
enc110,
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 600000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
index 00a7b65d9809..863641ca07a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_link_encoder.o dce80_opp.o \
+DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_opp.o \
dce80_opp_formatter.o dce80_opp_regamma.o \
dce80_timing_generator.o dce80_transform.o dce80_transform_gamut.o \
dce80_transform_scl.o dce80_opp_csc.o\
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
deleted file mode 100644
index bd364eeb6916..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "dce80_link_encoder.h"
-#include "stream_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-#include "i2caux_interface.h"
-
-/* TODO: change to dce80 header file */
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dce/dce_11_0_enum.h"
-
-#define LINK_REG(reg)\
- (enc110->link_regs->reg)
-
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLK 600000
-
-#define DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 297000
-
-#define DEFAULT_AUX_MAX_DATA_SIZE 16
-#define AUX_MAX_DEFER_WRITE_RETRY 20
-/*
- * @brief
- * Trigger Source Select
- * ASIC-dependent, actual values for register programming
- */
-#define DCE80_DIG_FE_SOURCE_SELECT_INVALID 0x0
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGA 0x01
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGB 0x02
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGC 0x04
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGD 0x08
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGE 0x10
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGF 0x20
-
-/* all values are in milliseconds */
-/* For eDP, after power-up/power/down,
- * 300/500 msec max. delay from LCDVCC to black video generation */
-#define PANEL_POWER_UP_TIMEOUT 300
-#define PANEL_POWER_DOWN_TIMEOUT 500
-#define HPD_CHECK_INTERVAL 10
-
-/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-#define TMDS_MIN_PIXEL_CLOCK 25000
-/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-#define TMDS_MAX_PIXEL_CLOCK 165000
-
-enum {
- DP_MST_UPDATE_MAX_RETRY = 50
-};
-
-static enum bp_result link_transmitter_control(
- struct dce110_link_encoder *enc110,
- struct bp_transmitter_control *cntl)
-{
- enum bp_result result;
- struct dc_bios *bp = enc110->base.ctx->dc_bios;
-
- result = bp->funcs->transmitter_control(bp, cntl);
-
- return result;
-}
-
-static void dce80_link_encoder_enable_tmds_output(
- struct link_encoder *enc,
- enum clock_source_id clock_source,
- enum dc_color_depth color_depth,
- bool hdmi,
- bool dual_link,
- uint32_t pixel_clock)
-{
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- struct dc_context *ctx = enc110->base.ctx;
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* Enable the PHY */
-
- cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = enc->preferred_engine;
- cntl.transmitter = enc110->base.transmitter;
- cntl.pll_id = clock_source;
- if (hdmi) {
- cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- cntl.lanes_number = 4;
- } else if (dual_link) {
- cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
- cntl.lanes_number = 8;
- } else {
- cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- cntl.lanes_number = 4;
- }
- cntl.hpd_sel = enc110->base.hpd_source;
-
- cntl.pixel_clock = pixel_clock;
- cntl.color_depth = color_depth;
-
- result = link_transmitter_control(enc110, &cntl);
-
- if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
- "%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- }
-}
-
-static void configure_encoder(
- struct dce110_link_encoder *enc110,
- const struct dc_link_settings *link_settings)
-{
- struct dc_context *ctx = enc110->base.ctx;
- uint32_t addr;
- uint32_t value;
-
- /* set number of lanes */
- addr = LINK_REG(DP_CONFIG);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
- DP_CONFIG, DP_UDI_LANES);
- dm_write_reg(ctx, addr, value);
-
-}
-
-/* enables DP PHY output */
-static void dce80_link_encoder_enable_dp_output(
- struct link_encoder *enc,
- const struct dc_link_settings *link_settings,
- enum clock_source_id clock_source)
-{
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- struct dc_context *ctx = enc110->base.ctx;
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* Enable the PHY */
-
- /* number_of_lanes is used for pixel clock adjust,
- * but it's not passed to asic_control.
- * We need to set number of lanes manually.
- */
- configure_encoder(enc110, link_settings);
-
- cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = enc->preferred_engine;
- cntl.transmitter = enc110->base.transmitter;
- cntl.pll_id = clock_source;
- cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
- cntl.lanes_number = link_settings->lane_count;
- cntl.hpd_sel = enc110->base.hpd_source;
- cntl.pixel_clock = link_settings->link_rate
- * LINK_RATE_REF_FREQ_IN_KHZ;
- /* TODO: check if undefined works */
- cntl.color_depth = COLOR_DEPTH_UNDEFINED;
-
- result = link_transmitter_control(enc110, &cntl);
-
- if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
- "%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- }
-}
-
-static const struct link_encoder_funcs dce80_lnk_enc_funcs = {
- .validate_output_with_stream =
- dce110_link_encoder_validate_output_with_stream,
- .hw_init = dce110_link_encoder_hw_init,
- .setup = dce110_link_encoder_setup,
- .enable_tmds_output = dce80_link_encoder_enable_tmds_output,
- .enable_dp_output = dce80_link_encoder_enable_dp_output,
- .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
- .disable_output = dce110_link_encoder_disable_output,
- .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
- .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
- .update_mst_stream_allocation_table =
- dce110_link_encoder_update_mst_stream_allocation_table,
- .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- .set_dmcu_backlight_level =
- dce110_link_encoder_set_dmcu_backlight_level,
- .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level,
- .backlight_control = dce110_link_encoder_edp_backlight_control,
- .power_control = dce110_link_encoder_edp_power_control,
- .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
- .destroy = dce110_link_encoder_destroy
-};
-
-bool dce80_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs)
-{
- struct graphics_object_encoder_cap_info enc_cap_info = {0};
-
- enc110->base.funcs = &dce80_lnk_enc_funcs;
- enc110->base.ctx = init_data->ctx;
- enc110->base.id = init_data->encoder;
-
- enc110->base.hpd_source = init_data->hpd_source;
- enc110->base.connector = init_data->connector;
- enc110->base.input_signals = SIGNAL_TYPE_ALL;
-
- enc110->base.adapter_service = init_data->adapter_service;
-
- enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-
- enc110->base.features.flags.raw = 0;
-
- enc110->base.transmitter = init_data->transmitter;
-
- enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
-
- enc110->base.features.max_pixel_clock = MAX_ENCODER_CLK;
-
- enc110->base.features.max_hdmi_pixel_clock =
- DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
- enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
- enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-
- /* set the flag to indicate whether driver poll the I2C data pin
- * while doing the DP sink detect
- */
-
- if (dal_adapter_service_is_feature_supported(enc110->base.adapter_service,
- FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
- enc110->base.features.flags.bits.
- DP_SINK_DETECT_POLL_DATA_PIN = true;
-
- enc110->base.output_signals =
- SIGNAL_TYPE_DVI_SINGLE_LINK |
- SIGNAL_TYPE_DVI_DUAL_LINK |
- SIGNAL_TYPE_LVDS |
- SIGNAL_TYPE_DISPLAY_PORT |
- SIGNAL_TYPE_DISPLAY_PORT_MST |
- SIGNAL_TYPE_EDP |
- SIGNAL_TYPE_HDMI_TYPE_A;
-
- /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
- * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
- * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
- * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
- * Prefer DIG assignment is decided by board design.
- * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
- * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
- * By this, adding DIGG should not hurt DCE 8.0.
- * This will let DCE 8.1 share DCE 8.0 as much as possible
- */
-
- enc110->link_regs = link_regs;
- enc110->aux_regs = aux_regs;
- enc110->hpd_regs = hpd_regs;
-
- switch (enc110->base.transmitter) {
- case TRANSMITTER_UNIPHY_A:
- enc110->base.preferred_engine = ENGINE_ID_DIGA;
- break;
- case TRANSMITTER_UNIPHY_B:
- enc110->base.preferred_engine = ENGINE_ID_DIGB;
-
- break;
- case TRANSMITTER_UNIPHY_C:
- enc110->base.preferred_engine = ENGINE_ID_DIGC;
- break;
- case TRANSMITTER_UNIPHY_D:
- enc110->base.preferred_engine = ENGINE_ID_DIGD;
- break;
- case TRANSMITTER_UNIPHY_E:
- enc110->base.preferred_engine = ENGINE_ID_DIGE;
- break;
- case TRANSMITTER_UNIPHY_F:
- enc110->base.preferred_engine = ENGINE_ID_DIGF;
- break;
- default:
- ASSERT_CRITICAL(false);
- enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
- break;
- }
-
- dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX,
- "Using channel: %s [%d]\n",
- DECODE_CHANNEL_ID(init_data->channel),
- init_data->channel);
-
- /* Override features with DCE-specific values */
- if (dal_adapter_service_get_encoder_cap_info(
- enc110->base.adapter_service,
- enc110->base.id, &enc_cap_info))
- enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
- enc_cap_info.dp_hbr2_cap;
-
- /* test pattern 3 support */
- enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
- enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-
- enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
- dal_adapter_service_is_feature_supported(enc110->base.adapter_service,
- FEATURE_SUPPORT_DP_Y_ONLY);
-
- enc110->base.features.flags.bits.IS_YCBCR_CAPABLE =
- dal_adapter_service_is_feature_supported(enc110->base.adapter_service,
- FEATURE_SUPPORT_DP_YUV);
-
- return true;
-}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
deleted file mode 100644
index 326409bc159c..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_LINK_ENCODER__DCE80_H__
-#define __DC_LINK_ENCODER__DCE80_H__
-
-#include "link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-
-bool dce80_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs);
-
-#endif /* __DC_LINK_ENCODER__DCE80_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index d557fcc40ccb..0023ed344467 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -23,6 +23,7 @@
*
*/
+
#include "dm_services.h"
#include "link_encoder.h"
@@ -36,12 +37,11 @@
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_resource.h"
#include "dce80/dce80_timing_generator.h"
-#include "dce80/dce80_link_encoder.h"
-#include "dce110/dce110_link_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce80/dce80_mem_input.h"
#include "dce80/dce80_ipp.h"
#include "dce80/dce80_transform.h"
-#include "dce/dce110_stream_encoder.h"
#include "dce80/dce80_opp.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_clock_source.h"
@@ -504,13 +504,17 @@ struct link_encoder *dce80_link_encoder_create(
if (!enc110)
return NULL;
- if (dce80_link_encoder_construct(
+ if (dce110_link_encoder_construct(
enc110,
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 297000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
index 02fa1d24f7f0..9667f00e9447 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
@@ -64,6 +64,7 @@ struct encoder_feature_support {
/* maximum supported clock */
unsigned int max_pixel_clock;
unsigned int max_hdmi_pixel_clock;
+ bool ycbcr420_supported;
};
enum physical_phy_id {
--
2.10.1
