From: Tony Cheng <tony.cheng@xxxxxxx>
- also fix force_hw_base_light_sleep. wrong DCE version is hooked up
- fix previous commit underlay isn't powered up when FE is powered up
Signed-off-by: Tony Cheng <tony.cheng at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 39 ++++++++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 72 +++++++++++---
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 26 -----
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 4 +-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 5 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 24 ++---
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 2 -
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 4 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 3 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 6 +-
drivers/gpu/drm/amd/dal/dc/gpu/Makefile | 6 +-
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 110 ---------------------
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h | 33 -------
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c | 89 -----------------
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h | 33 -------
.../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c | 52 ----------
.../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h | 31 ------
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 3 -
18 files changed, 119 insertions(+), 423 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
index 80f827ba63b4..3a453bf395bb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -122,3 +122,42 @@ void dce_set_blender_mode(struct dce_hwseq *hws,
BLND_MODE, blnd_mode,
BLND_MULTIPLIED_MODE, multiplied_mode);
}
+
+
+static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
+{
+ if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
+ REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
+ DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
+}
+
+static void dce_underlay_clock_enable(struct dce_hwseq *hws)
+{
+ /* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
+ if (REG(DCFEV_CLOCK_CONTROL))
+ REG_UPDATE(DCFEV_CLOCK_CONTROL,
+ DCFEV_CLOCK_ENABLE, 1);
+}
+
+static void enable_hw_base_light_sleep(void)
+{
+ /* TODO: implement */
+}
+
+static void disable_sw_manual_control_light_sleep(void)
+{
+ /* TODO: implement */
+}
+
+void dce_clock_gating_power_up(
+ struct dce_hwseq *hws,
+ bool enable)
+{
+ if (enable) {
+ enable_hw_base_light_sleep();
+ disable_sw_manual_control_light_sleep();
+ } else {
+ dce_disable_sram_shut_down(hws);
+ dce_underlay_clock_enable(hws);
+ }
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
index 11bff8750999..5ec78dcad9b5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -41,7 +41,8 @@
SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
- SRII(DCFE_CLOCK_CONTROL, DCFE, 5)
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
#define HWSEQ_BLND_REG_LIST() \
SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
@@ -57,9 +58,40 @@
SRII(BLND_CONTROL, BLND, 4), \
SRII(BLND_CONTROL, BLND, 5)
-#define HWSEQ_DCE8_REG_LIST_BASE() \
+#define HWSEQ_DCE11_REG_LIST_BASE() \
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+ SR(DCFEV_CLOCK_CONTROL), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
+ SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
+ SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
+ SRII(BLND_CONTROL, BLND, 0),\
+ SRII(BLND_CONTROL, BLND, 1),\
+ SR(BLNDV_CONTROL)
+
+#define HWSEQ_DCE8_REG_LIST() \
HWSEQ_DCEF_REG_LIST_DCE8(), \
- HWSEQ_BLND_REG_LIST(), \
+ HWSEQ_BLND_REG_LIST()
+
+#define HWSEQ_ST_REG_LIST() \
+ HWSEQ_DCE11_REG_LIST_BASE(), \
+ .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
+ .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
+ .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
+ .BLND_CONTROL[2] = mmBLNDV_CONTROL,
+
+#define HWSEQ_CZ_REG_LIST() \
+ HWSEQ_DCE11_REG_LIST_BASE(), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
+ SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
+ SRII(BLND_CONTROL, BLND, 2), \
+ .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
+ .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
+ .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
+ .BLND_CONTROL[3] = mmBLNDV_CONTROL
#define HWSEQ_COMMON_REG_LIST_BASE() \
HWSEQ_DCEF_REG_LIST(), \
@@ -67,6 +99,8 @@
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
+ uint32_t DCFEV_CLOCK_CONTROL;
+ uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
uint32_t BLND_V_UPDATE_LOCK[6];
uint32_t BLND_CONTROL[6];
uint32_t BLNDV_CONTROL;
@@ -77,7 +111,8 @@ struct dce_hwseq_registers {
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
- HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh)
+ HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
+ SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
@@ -90,19 +125,28 @@ struct dce_hwseq_registers {
HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
-#define HWSEQ_DCE8_MASK_SH_LIST_BASE(mask_sh)\
+#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh)
-#define HWSEQ_COMMON_MASK_SH_LIST_BASE(mask_sh)\
+#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_)
+#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+ SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh)
+
+#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCE10_MASK_SH_LIST(mask_sh)
+
#define HWSEQ_REG_FIED_LIST(type) \
type DCFE_CLOCK_ENABLE; \
+ type DCFEV_CLOCK_ENABLE; \
+ type DC_MEM_GLOBAL_PWR_REQ_DIS; \
type BLND_DCP_GRPH_V_UPDATE_LOCK; \
type BLND_SCL_V_UPDATE_LOCK; \
type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
@@ -133,6 +177,12 @@ struct dce_hwseq {
struct dce_hwseq_wa wa;
};
+enum blnd_mode {
+ BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+};
+
void dce_enable_fe_clock(struct dce_hwseq *hwss,
unsigned int inst, bool enable);
@@ -141,12 +191,10 @@ void dce_pipe_control_lock(struct dce_hwseq *hws,
enum pipe_lock_control control_mask,
bool lock);
-enum blnd_mode {
- BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLND_MODE_STEREO
-};
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst, enum blnd_mode mode);
+
+void dce_clock_gating_power_up(struct dce_hwseq *hws,
+ bool enable);
+
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index a7fa7ede2ec2..e2fe024e1182 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -122,30 +122,6 @@ static void set_bandwidth(struct core_dc *dc)
/* Do nothing until we have proper bandwitdth calcs */
}
-static void enable_hw_base_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void disable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void enable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep();
- disable_sw_manual_control_light_sleep();
- } else {
- enable_sw_manual_control_light_sleep();
- }
-}
/**************************************************************************/
@@ -154,8 +130,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
dce110_hw_sequencer_construct(dc);
/* TODO: dce80 is empty implementation at the moment*/
- dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce100_power_up;
-
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc->hwss.set_displaymarks = set_displaymarks;
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 2451327de092..4b8c1e79caaa 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -455,11 +455,11 @@ static const struct dce_hwseq_registers hwseq_reg = {
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_DCE10_MASK_SH_LIST(_MASK)
};
static struct dce_hwseq *dce100_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 10b55e77ecc0..7ebe090c75f2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -33,8 +33,6 @@
#include "dce110_hw_sequencer.h"
#include "dce110_timing_generator.h"
-#include "gpu/dce110/dc_clock_gating_dce110.h"
-
#include "bios/bios_parser_helper.h"
#include "timing_generator.h"
#include "mem_input.h"
@@ -1677,7 +1675,7 @@ static void init_hw(struct core_dc *dc)
true);
}
- dc->hwss.clock_gating_power_up(dc->ctx, false);
+ dce_clock_gating_power_up(dc->hwseq, false);;
/***************************************/
for (i = 0; i < dc->link_count; i++) {
@@ -1996,7 +1994,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
- .clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
.set_display_clock = dce110_set_display_clock,
.set_displaymarks = dce110_set_displaymarks,
.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index e19a69419c5c..3572301e09c0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -426,38 +426,32 @@ static struct stream_encoder *dce110_stream_encoder_create(
.reg_name[id] = mm ## block ## id ## _ ## reg_name
#define HWSEQ_DCE11_REG_LIST_BASE() \
- HWSEQ_DCEF_REG_LIST(),\
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+ SR(DCFEV_CLOCK_CONTROL), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
SRII(BLND_CONTROL, BLND, 0),\
SRII(BLND_CONTROL, BLND, 1),\
- .BLNDV_CONTROL = mmBLNDV_CONTROL
+ SR(BLNDV_CONTROL)
static const struct dce_hwseq_registers hwseq_stoney_reg = {
- HWSEQ_DCE11_REG_LIST_BASE(),
- .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END,
- .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK,
- .BLND_CONTROL[2] = mmBLNDV_CONTROL,
+ HWSEQ_ST_REG_LIST()
};
static const struct dce_hwseq_registers hwseq_cz_reg = {
- HWSEQ_DCE11_REG_LIST_BASE(),
- SRII(CRTC_H_BLANK_START_END, CRTC, 2),
- SRII(BLND_V_UPDATE_LOCK, BLND, 2),
- SRII(BLND_CONTROL, BLND, 2),
- .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END,
- .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK,
- .BLND_CONTROL[3] = mmBLNDV_CONTROL,
+ HWSEQ_CZ_REG_LIST()
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT),
+ HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK),
+ HWSEQ_DCE11_MASK_SH_LIST(_MASK),
};
static struct dce_hwseq *dce110_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index 4021b0b1e3a9..1b5182a0c79e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -30,7 +30,6 @@
#include "dce112_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
-#include "gpu/dce112/dc_clock_gating_dce112.h"
/* include DCE11.2 register header files */
#include "dce/dce_11_2_d.h"
@@ -196,7 +195,6 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
dce110_hw_sequencer_construct(dc);
dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
- dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 01534872d3b8..514669153910 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -480,11 +480,11 @@ static const struct dce_hwseq_registers hwseq_reg = {
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_DCE112_MASK_SH_LIST(_MASK)
};
static struct dce_hwseq *dce112_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
index a69e609b9e75..c7a2b768bcd1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
@@ -32,8 +32,6 @@
#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
-#include "gpu/dce80/dc_clock_gating_dce80.h"
-
/* include DCE8 register header files */
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
@@ -132,7 +130,6 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
{
dce110_hw_sequencer_construct(dc);
- dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce80_power_up;
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc->hwss.set_displaymarks = set_displaymarks;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 100c8c01aa21..1279136d1764 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -442,15 +442,15 @@ static struct stream_encoder *dce80_stream_encoder_create(
.reg_name[id] = mm ## block ## id ## _ ## reg_name
static const struct dce_hwseq_registers hwseq_reg = {
- HWSEQ_DCE8_REG_LIST_BASE()
+ HWSEQ_DCE8_REG_LIST()
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_DCE8_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_DCE8_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_DCE8_MASK_SH_LIST(_MASK)
};
static struct dce_hwseq *dce80_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
index 06f405a6cf45..ec2ef4994ade 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
@@ -12,7 +12,7 @@ AMD_DAL_FILES += $(AMD_DAL_GPU)
###############################################################################
# DCE 80 family
###############################################################################
-GPU_DCE80 = display_clock_dce80.o dc_clock_gating_dce80.o
+GPU_DCE80 = display_clock_dce80.o
AMD_DAL_GPU_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpu/dce80/,$(GPU_DCE80))
@@ -22,13 +22,13 @@ AMD_DAL_FILES += $(AMD_DAL_GPU_DCE80)
###############################################################################
# DCE 110 family
###############################################################################
-GPU_DCE110 = display_clock_dce110.o dc_clock_gating_dce110.o
+GPU_DCE110 = display_clock_dce110.o
AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110)
-GPU_DCE112 = display_clock_dce112.o dc_clock_gating_dce112.o
+GPU_DCE112 = display_clock_dce112.o
AMD_DAL_GPU_DCE112 = $(addprefix $(AMDDALPATH)/dc/gpu/dce112/,$(GPU_DCE112))
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
deleted file mode 100644
index 19543db48f99..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/logger_interface.h"
-
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dc_clock_gating_dce110.h"
-
-/******************************************************************************
- * Macro definitions
- *****************************************************************************/
-
-#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL( \
- "%s:%s()\n", __FILE__, __func__)
-
-/******************************************************************************
- * static functions
- *****************************************************************************/
-static void force_hw_base_light_sleep(struct dc_context *ctx)
-{
- uint32_t addr = 0;
- uint32_t value = 0;
-
- addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
- /* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
- * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 1,
- DC_MEM_GLOBAL_PWR_REQ_CNTL,
- DC_MEM_GLOBAL_PWR_REQ_DIS);
-
- dm_write_reg(ctx, addr, value);
-
-}
-
-static void underlay_clock_enable(struct dc_context *ctx)
-{
- uint32_t value = 0;
-
- value = dm_read_reg(ctx, mmDCFEV_CLOCK_CONTROL);
-
- set_reg_field_value(
- value,
- 1,
- DCFEV_CLOCK_CONTROL,
- DCFEV_CLOCK_ENABLE);
-
- dm_write_reg(ctx, mmDCFEV_CLOCK_CONTROL, value);
-}
-
-static void enable_hw_base_light_sleep(struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-static void disable_sw_manual_control_light_sleep(
- struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-/******************************************************************************
- * public functions
- *****************************************************************************/
-
-void dal_dc_clock_gating_dce110_power_up(
- struct dc_context *ctx,
- bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep(ctx);
- disable_sw_manual_control_light_sleep(ctx);
- } else {
- force_hw_base_light_sleep(ctx);
- underlay_clock_enable(ctx);
- }
-
-#if 0
- if (ctx->dc->debug.disable_clock_gate)
- return; /* clock gating not implemented so nothing to disable */
-#endif
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
deleted file mode 100644
index 1bfd75a1fb51..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DC_CLOCK_GATING_DCE110_H__
-#define __DAL_DC_CLOCK_GATING_DCE110_H__
-
-void dal_dc_clock_gating_dce110_power_up(
- struct dc_context *ctx,
- bool enable);
-
-#endif /* __DAL_DC_CLOCK_GATING_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
deleted file mode 100644
index cef5008cd08d..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/logger_interface.h"
-
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-#include "dc_clock_gating_dce112.h"
-
-/******************************************************************************
- * Macro definitions
- *****************************************************************************/
-
-#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(\
- "%s:%s()\n", __FILE__, __func__)
-
-/******************************************************************************
- * static functions
- *****************************************************************************/
-static void force_hw_base_light_sleep(struct dc_context *ctx)
-{
- uint32_t addr = 0;
- uint32_t value = 0;
-
- addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
- /* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
- * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 1,
- DC_MEM_GLOBAL_PWR_REQ_CNTL,
- DC_MEM_GLOBAL_PWR_REQ_DIS);
-
- dm_write_reg(ctx, addr, value);
-
-}
-
-static void enable_hw_base_light_sleep(struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-static void disable_sw_manual_control_light_sleep(
- struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-/******************************************************************************
- * public functions
- *****************************************************************************/
-
-void dal_dc_clock_gating_dce112_power_up(
- struct dc_context *ctx,
- bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep(ctx);
- disable_sw_manual_control_light_sleep(ctx);
- } else {
- force_hw_base_light_sleep(ctx);
- }
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
deleted file mode 100644
index 118da647de18..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DC_CLOCK_GATING_DCE112_H__
-#define __DAL_DC_CLOCK_GATING_DCE112_H__
-
-void dal_dc_clock_gating_dce112_power_up(
- struct dc_context *ctx,
- bool enable);
-
-#endif /* __DAL_DC_CLOCK_GATING_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
deleted file mode 100644
index 5f575770f42e..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dc_clock_gating_dce80.h"
-
-static void enable_hw_base_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void disable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void enable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-void dal_dc_clock_gating_dce80_power_up(struct dc_context *ctx, bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep();
- disable_sw_manual_control_light_sleep();
- } else {
- enable_sw_manual_control_light_sleep();
- }
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
deleted file mode 100644
index f4111c5a5e63..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DC_CLOCK_GATING_DCE80_H__
-#define __DAL_DC_CLOCK_GATING_DCE80_H__
-
-void dal_dc_clock_gating_dce80_power_up(struct dc_context *ctx, bool enable);
-
-#endif /* __DAL_DC_CLOCK_GATING_DCE80_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index dcaac8a336d1..e568ed891a06 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -98,9 +98,6 @@ struct hw_sequencer_funcs {
void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t);
- /* power management */
- void (*clock_gating_power_up)(struct dc_context *ctx, bool enable);
-
void (*enable_display_pipe_clock_gating)(
struct dc_context *ctx,
bool clock_gating);
--
2.10.1
